I am seeing a fixed DC offset in the output of adc when it is set in LVCMOS mode vs when it is set in LVDS output mode. When I give input as sine wave of 10dBm 1MHz frequency, the output of LVCMOS mode is centered at 0 . However, when the adc output mode is set as LVCMOS, the output comes out above (2^13), though the shape is retained correctly. I am suspecting that the parallel LVCMOS mode is not removing the dc offset.
Also when I give no input to channel A, I am expecting the lower 2-3 bits to be triggered rest all should be 0. This is observed for LVDS mode, but in CMOS mode, 2-3 bits are triggered and rest all are fixed at HIGH.
Is there a way to overcome this issue or some register settings for ADC to be set. I have already tried 'Enable Offset Correction' for ADC but did not work.