ADS1278-HT: Driving the ADC with a low bandwidth op amp - opa2333-HT

Hi Martin,

We could look into this detail for you.  You are correct, the low bandwidth of the OPA2333-HT could potentially be a limitation; however, as you have mentioned, since you are setting the ADS1278 with fclk=1-MHz, in the Low-Speed mode with a lower modulator frequency of  fmod=1-MHz/40, this may be possible. I will need to verify this on simulation.

Per your post on the ADC forum, it appears you require operation at +165-C, hence you require the High Temp grade devices.  

Is the OPA2333 set-up in buffer, or gain configuration, or inverting configuration?  What voltage supplies, the input voltage common-mode requirement, input signal amplitude, and what reference voltage is used for the ADS1278? Is the input signal a DC or AC signal? if AC, what is the frequency range?  If you have a preliminary schematic showing the OPA2333-HT circuit, this would be helpful and we could look into this, verify that the circuit works, and optimize the RC filter between the OPA2333-HT and ADS1278-HT.

Thank you and Kind Regards,

Luis 

HI Martin,

When using the device in Low-Speed mode, with fclk=1-MHz, the output data rate is Data Rate (SPS)=1-MHz/2560=~390SPS (per table 10 of the datasheet). The normalized frequency response of the digital filter scales with the modulator frequency.  Looking at Figure 55, if the device is used with fclock=1-MHz, in low-speed mode, with clk-div-1, the output data rate is 390-Hz, and the BW of  the digital filter is approximately ~(0.453)*(390Hz) or 176-Hz.

The trade-off between using CLKDIV = 1 and CLKDIV=0 is in the speed and input impedance of the device as shown on table 9, table 10 and figure 66.  When using low speed with clk-div=1, the modulator samples at a slower frequency of fmod=fclk/40, providing a higher input impedance.  The relation between the average or effective input impedance and modulator frequency is given on figure 66.   

Thank you and Regards,

Luis

Hi Luis

Many thanks for your prompt reply and drawing my attention to the input impedance trade off.

I'm also interested in confirming the suitability of a using a low bandwidth op amp OPA2333-HT (this is a high temperature application) with the ADS1278-HT if Fmod is a relatively low speed

so essentially my questions are

1) are the switched capacitors on the input toggling at 25Khz (ie fclk/40)?

2) if this is the case is the 350kHz OPA2333-HT a suitable driver for the ADC?

Note: i plan on having AINN tied to a buffed Vcom, AINP will be a 0-5V signal centred around 2.5V driven by the OPA2333-HT. 

Kind Regards

Martin