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ADC34J23: Data-format of ADC34J23

Hiroaki Kawamoto
Prodigy 70 points
Part Number: ADC34J23

Hi,

I tried caputuring the data from ADC34J23.

9 ~ 12bit of any sample in any lane is always 0.

I think it doesnt make sense however the data is padded by 0.

I am waiting for your advice.

Best regards,

Hiroaki Kawamoto.

  • 0
    TI__Genius 12780 points

    Hi Hiroaki,

    Is there an analog input signal present, or is this an idle channel measurement? Can you share a picture?

    Have you tried using the digital ramp test pattern? This will help to ensure that the FPGA is setup accordingly. The below register writes will enable the digital ramp pattern for channel A. See page 64 and 65 of the datasheet for more information.

    0x06 0x02 #Enable Test Pattern

    0x0A 0x40# Enable CHA Digital Ramp Test Pattern

    Best Regards,

    Dan

  • 0 in reply to dBrock
    TI__Genius 12780 points

    Hi Hiroaki,

    I will go ahead and close this thread due to inactivity. Please open a new post if further assistance is required.

    Best Regards,

    Dan