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ADS4149: DC bias of inputs with AC-coupled signals.

Part Number: ADS4149

Hello,

We are using the ADS4149 as a digitizer for unipolar PMT pulses and therefor would like to bias the inputs towards one end of the range.  We are presently using some op-amps (well filtered outputs) to provide a stiff voltage both above and below Vcm.  These bias voltages are couple to the ADC inputs through 50ohm "termination" resistors, while the input is AC coupled.  We see 60MHz noise (1/4 sampling freq. and dominant FPGA noise) that is proportional to the amount of DC offset applied (up to ~10LSB rms).  I am about to reconfigure the DC bias network to be referenced off of Vcm, but wondering if others have used DC biasing or know of any "gotchas" with using the Vcm pin as a reference for a symmetric DC bias. 
Thanks for any insight!

-Perry

  • Perry,

    This could be caused by noise on the bias voltages. Make sure these are clean as well as the clock source to the ADC. 

    Regards,

    Jim

      

  • Hi Jim,

    Thanks for the quick reply.- you were right on both counts! 
    We did find some 60MHz phase noise on the sampling clock and the bias supplies got filtered better. 
    Getting rid of the 3.6nH inductors in datasheet example also seemed to help. We are now down to about 3LSB rms noise at midspan and about 6LSB when biased at each end of input range
    I am now wondering if perhaps the example 2x25 Ohm + 5pF snubber network shown in datasheet can also be eliminated?.
    We will have a 47pF 0603-size cap right across the input.  Is there anything special about that RC network for a "low" input BW application (still sampling at 250Msps).

    Do you ever see people use LC differential bandpass filters on the clock inputs with these types of ADCs?

    Thanks!

    -Perry

  • Perry,

    The R-C-R filter is used to absorb sampling glitches. Suggest leaving this in since you are sampling at such a high rate. Also suggest filtering the VCM input.

    I have not seen any diff bandpass filter applications on the input clock. If you are thinking about this, it is very important to keep the phase and amplitude balanced of both legs of the filter output.

    Also suggest not enabling the High Performance mode is this works best with a low sample rate and high IF.

    Regards,

    Jim