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ADC12J1600: JESD204B captured data

Part Number: ADC12J1600
Other Parts Discussed in Thread: ADC12DJ3200EVM, ADC12J4000EVM

Dear TI experts

I'm trying to build the connection between ADC12J1600 and KC705 using the JESD204B protocol. As for now, the data can be sampled by ADC and captured on HSDC Pro software.

I'm trying to send the data onto FPGA, I've downloaded a JESD204B demo project on board. But it looks like the transceiver is in PMA loopback mood, so the receiver's ILA is not capturing the sampled data from outside but a pre-generated sine wave that is attached to this project.

Could you please take a review of this demo project and show me the right way to set it up, so that the FPGA can receive the sampled data by ADC?

Here is the specification of my ADC12J1600's setup: Decimated by 4, DDR=1, P54=1, LMF=422.

Huge appreciation for your help in advance.

Best,

Haotian

JESD204_Hardware_Demo_2016_1_v2.zip

  • Haotian,

    This project was designed by Xilinx and was intended to be a loop back example. It was never designed to be integrated with HSDC pro nor used with an external ADC board as far as I can tell. 

    The source code that can be found under the TSW14J10EVM product folder works with the ADC12J1600 and HSDC Pro, which also is not what you want I am guessing.

    We also have Xilinx example source code that can be found under the ADC12DJ3200EVM product folder that is based off of the KCU105 that may be of help. This code captured data using Chipscope instead of using the HSDC Pro GUI, which is usually what a customer is looking for.

    I think your best bet is to somehow combine these three projects to get what you need. You may also want to look at the Xilinx website for more examples that you could use.

    Regards,

    Jim 

  • Hi Jim,

    I really appreciate your quick response>

    I want to make sure I can use the JESD reference design for TSW14J10 to build the connection between TSW14J10 and KC705, can't I? The reason I try to search for another JESD example is, I think ILA can be easier to use compared to Microblaze.

    Another quick question is since I already know my Ref_clk=200Mhz, Core_clk=100Mhz, am I supposed to change the value of these two clock signals in the XDC file?

    Best,

    Haotian

  • Haotian,

    I think so. It has been a long time since I worked with this.

    Regards,

    Jim

  • Hi Jim,

    I'm trying to implement the JESD204_TI_reference design, but I'm new to use SDK. I've followed the steps to build the reference design, here's what I've done:

    1. Generate the bitstream and export the project into SDK;

    2. In SDK, build a new application project and name it "tsw", copy the tsw file in sw_src into proj_kc705/proj_kc705.sdk/tsw;

    3. Program the FPGA in SDK and configure the application as shown in the screenshots:

    Then I run the application, but I got the error like this:

    I'm wondering have you ever met this error before? Could you tell me how to fix it? I've searched on the Xilinx forum, and someone said it might need to change the setup in bsp files, I'm not sure if that's the right way.

    Thanks,

    Haotian.

  • Haotian,

    I have not seen these issues before. You need to contact Xilinx about this. Try using their website help site for this. They have their own version of E2E. This may be better than the forum.

    Regards,

    Jim

  • Hi Jim

    A quick question, I'm editing the XDC file for FPGA to receive the sampled data. Should I follow the information below:

    I'm asking about that because the pin placement listed in this table is different from the XDC file in the JESD_TI_Reference_Design you sent to me. So I'm a little confused.

    Thanks in advance.

    Haotian.

  • BTW, the table comes from TSW14J10's user guide.

  • Haotian,

    This is the pinout to the FMC connector on the board, not the FPGA. The XDC file uses the FPGA pinout. You can use this table along with the KC705 schematic to determine which pins are used by the FPGA.

    Regards,

    Jim

    kc705_Schematic_xtp132_rev1_1.pdf

  • Hi Jim,

    I've built a simplified JESD project based on the Xilinx JESD204b_demo project, which only has one JESD receiver. It seems to be able to capture data from external signals. I was setting the ADC12J1600 to test pattern mode, but the result doesn't look correct. I made a summary of all the configuration I set for both ADC12J1600 and KC705.  I also attached the JESD project modified by myself. As for now, I'm not sure what can be the source of the errors. I'll appreciate if you can help me to check it.

    Thanks so much for your continuous help.

    Best,

    Haotian

    Here's the link of my project:5140.ADC12J1600+KC705.pptx

    drive.google.com/.../view

  • Haotian,

    Follow the instructions of the attached document to test the ADC in ramp test pattern mode. I did this with a KC705 and an ADC12J4000EVM. The ADC12J1600 instructions will be the same.

    Regards,

    Jim

    ADC12J1600_DEC_4_KC705_test_pattern_mode.pptx

  • Hi Jim,

    Thanks for your reply.

    There's one thing I just realized. When I used HSDC Pro, it will directly download the pre-generated bitstreams file of JESD204B_TI reference design onto the kc705 so that the host PC can read the sampled data through SPI. Am I right?

    In that case, if we want to apply our algorithm on FPGA, we have to integrate our own block of code with the reference design, generate the new bitstreams file and then replace the original bitstreams file included in HSDC Pro with the new file, I guess?

    If all I say above is correct, I'm wondering, is that possible if I want to directly send the serial data generated by ADC's transmitter onto KC705 by still using the TSW14J10?

    Best,

    Haotian.

  • Haotian,

    There's one thing I just realized. When I used HSDC Pro, it will directly download the pre-generated bitstreams file of JESD204B_TI reference design onto the kc705 so that the host PC can read the sampled data through SPI. Am I right? Correct.

    In that case, if we want to apply our algorithm on FPGA, we have to integrate our own block of code with the reference design, generate the new bitstreams file and then replace the original bitstreams file included in HSDC Pro with the new file, I guess? Correct, but not recommended.

    If all I say above is correct, I'm wondering, is that possible if I want to directly send the serial data generated by ADC's transmitter onto KC705 by still using the TSW14J10? See comments provided by Xilinx below regarding this firmware.

    "This reference design should not be used as an example for how to connect a specific ADC or DAC to a Xilinx FPGA. This reference design is capable of interfacing with all TI the FMC based ADC and DAC EVM’s. To do this the design complexity is much greater than is required to simply interface to an ADC or DAC running with a specific configuration and much of the design has been abstracted and placed under HSDC Pro software control.

    For a quick start to get your own design up and running. Refer to [1] Xilinx JESD204B LogiCORE IP Product Guide and start with the example design and demo testbench that is delivered when you generate a customized JESD204B core".

    Regards,

    Jim 

  • Hi Jim,

    Thanks for your reply, I've followed the instruction in your slides to do the ramp test. However, the data captured on FPGA is still incorrect. I've attached a report about the current status of my project, could you please check this file and give some feedback on what can be the cause of the error?

    Thanks in advance,

    Haotian.jesd204_debugging_report.docx

  • one thing I need to mention is since we need to develop our own algorithm on FPGA, so I didn't use HSDC Pro to capture the data but using logical analyzer on FPGA.

  • Haotian,

    We do not have the bandwidth to support you on this. Please try contacting Xilinx for more help with this.

    Regards,

    Jim