• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 3 answers
  • Subscribers 46 subscribers
  • Views 827 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

ADS5295: using 14x serialization.

ADS5295: About test pattern & sync pattern.

sungsik kang1
Prodigy 160 points

Part Number: ADS5295

I am using ADS5295 and I have some questions about the ADC's test pattern.!

Q1. On page 48 of the datasheet, Setting register 45h , D1=1 enables sync pattern mode.

     The datasheet does not mention the sync pattern.  Does this sync pattern mean "111111000000" or "0000001111111" ?  

 

Q2. If i set sync pattern mode, will the sync pattern output come from all 8 channels?

 

Q3. If i set ADC output format to 2's complement mode , does the  test pattern change?

     ( for example, test patten : 111111000000 ->  its 2's complement :000001000000 ) 

 

Q4. When i set register 46h D[11:9] : 0100 to use 14-bit serialization mode,  does the test pattern also change?

     ( if test pattern : 111111000000 (12bit) -> 11111110000000( 14bit)  ) 

 

Q5. What is the difference between a test pattern in register 45h and a test pattern in register 25h?

    I want to use test pattern to align data and clock in FPGA. Which register do i have to set?

 

 

Thank you for looking at the question.!

 

  • 0
    TI__Genius 12025 points

    Hi,

    This also continues and answers from the previous e2e questions.

    Please refer to the ADS5295 datasheet page 64 figure 61.

    This can help you understand more from your questions.

    Also we suggest you can order (please look at TI website) one ADS5295EVM with TSW1400EVM together

    then you can try all of your setting conditions as you mentioned.

    This can save you lot of time to try on your FPGA if you does not receive or capture

    the correct the serial data coming from LVDS output data.

    for your question 1, the sync pattern data should be half of serial output data (6bits) are '0'

    and the other serial output data (6bits) are '1'.

    We suggest you can order and measure from using ADS5295EVM and TSW1400EVM,

    then you can see any detail results which you are looking for.

    for question 2, all 8 channel output are the same from one channel to another channel.

    and you will capture all 8 output at the same time.

    for question 3, Test Pattern output won't get any effect by 2's complement mode.

    for question 4, please look at datasheet page 64 figure 61, Test Pattern data are fixed inside ADS5295 (only 12bits)

    so if your 12bit mode changed to 14bit mode in serialization block,

    then you should only receive two more '0' or '1' on your received serial data.

    for question 5, the most pattern which the customer used is Ramp Pattern mode.

    This is very easy to check and find out if you are capturing good or wrong pattern (data) or not.

    Thank you!

    Best regards,

    Chen

     

  • 0 in reply to Chen Kung
    Prodigy 160 points

    Hi!.

    First of all, thanks you very much for your kind explanation.

    As you say, i am considering buying evaluation board because i will use ads5295 in lots of project.

    Most of my questions have been solved, but one thing is still confusing.

    About question3.

    You said "Test Pattern output won't get any effect by 2's complement mode." This sentence is confusing to me.

    Does this mean that the test pattern is not changed to it's 2's complement in the output channel even if 2's complement mode is used?

    I think if the test pattern is 111000, the output from output channel is 001000 ( 2's complement of 111000). So, on the fpga side, I must accept the converted value.

    I wonder where the process of changing to a 2's component is done in Fig 61 on page 64. (before or after the test pattern.)

    Thanks.

  • 0 in reply to sungsik kang1
    TI__Genius 12025 points

    Hi,

    You are right!

    These details are not listed on the datasheet as you mentioned.

    But as we know since test pattern is used for checking out test conditions

    such as board, wire, and PC setup are correct or not,

    therefore when you set up the Test Pattern Mode,

    there are several register settings won't be useful such as Data Format.

    However, when you change Pattern Mode from such as Ramp Pattern or SYNC Pattern

    to  None, then Data Format (Offset Binary/2's Complement) will be active right away.

    They are not what result directly you can see

    until you need to run from the ADS5295EVM and TSW1400EVM

    and you can see the real output results.

    Thank you!

    Best regards,

    Chen

  • 0 in reply to Chen Kung
    Prodigy 160 points

    Thanks a lot!.

    It is a my last question!

    You said that 'sync test pattern' is fixed as 12 bit (111111000000).

    when i use 14x serialization, 2 more bit will be added.

    so,  where does 2 more bits are added? . to MSB? or LSB?

  • 0 in reply to sungsik kang1
    TI__Genius 12025 points

    Hi,

    Yes, you are right!

    When you are setting test pattern Mode (such as sync pattern),

    the device does not operate it like a signal.

    in this case if you even change from 12bit to 14bit serialization

    for example, Data format (such as 2' comp) won't take any action at all.

    so for this case, when you are setting the sync pattern

    when you set up 12bit serialization mode, you will capture the data from LVDS output as 111111000000

    when you set up 14bit serialization mode, you will capture the data from LVDS output as 11111110000000

    Therefore, when you are using test pattern,

    please don't expect the output data you will receive as the same as the Normal Mode (without using any pattern).

    These two methods (test pattern vs. without test pattern=normal) are not related to each other.

    Thank you!

    Best regards,

    Chen