Other Parts Discussed in Thread: ADS52J65, LMK04828, , LMK04821
Hello,
my company is interested in usage ADS52J65. I have already evaluated the EVM (rev A) board in TSW14J56 and now I would like to integrate it with our fpga platform so LMK and ADC will be configured through FMC slot.
I have questions about clocking ADc and SPI register sequence.
I presume the ADc on EVM uses LVDS clocking because SYSREF inputs need LVDS so there are phase matched for subclass 1. Board have unsoldered resistors R58/R62 (R68/R72) which I presume are for PECL what I would like to use for better clock phase noise performance. I'm not sure about default 82.5 ohm values. Should the values be 120/240 ohm? The differental R148/R157 should be removed if PECL is used?
Final configuration should be JESD204 in subclass 0, 125MSPS, LMK04828 in distribution mode (no PLL used) and internal DSP powered down (demodulator etc not used). I wanted use programmed registers by GUI as reference with datasheet for first try in our fpga platform but I was not able to do read back (maybe a bug in HSDC 5.0 what is not supported). The EVM package consists some configuration scripts so I believe all can be found in files:
Init.cfg
Analog Input.cfg
ADS52J65_JESD_2L_16x_16b_DPM 125M wo Decimation SubClass2.cfg
Is it right?
Thank you & Regards
Daniel