ADS1294R: Common Mode without Using RLD Electrode

Hi Damien,

Sorry for the delay in response. 

10M is fine. If unused, RLDIN & RLDREF should be tied to AVDD. 

Hi Damien,

Recommend decreasing C15 & C17 to 470pF to increase the high pass cutoff frequency above 60Hz. 

The biasing creating by R12, 29, 32 ,33 is redundant with the RLD drive. Both of these will be driving mid-supply and resistor tolerances may force these two sources to compete. I recommend removing one of them, but make the biasing connection to the left of R30 and R31 such that if they are populated with a value that is not 0ohm, they will be included in the feedback loop. This connection should be the same on the second input channel. Additionally, consider adding an RC filter to the second channel, after the common-mode connection and before the input pins of the device. 

Hi Damien,

This will be part of the anti-aliasing filter. It depends on what type of noise you anticipate being in the measurement, the sampling rate, and the delta-sigma modulator frequency. 

Using 22.1k and 47pF as shown at the end of PDK user's guide would be fine. The additional 10k and 47pF capacitor is not necessary, but some customers prefer to have greater attenuation of higher frequency signals so they go with a second order filter. . 

Hi Damien,

Happy to help! 

I think one of my previous comments may have been misinterpreted so I will try to explain in greater detail. 

Having two methods for biasing the input is redundant and I recommend removing one of them. 

The first method I see on your schematic is formed using AVDD, AVSS, R44, R45, R48, R49, R12, R29, R32, and R33. 

The second method I see on your schematic is formed using the RLD output of the device, R74, R75, R73, and R56. 

You should use one of these methods, but not both. Using both methods will result in them competing against each other due to resistor tolerance. i.e. method one biases to 1.64V and method two biases to 1.66V. By themselves, this small difference is not an issue - but with both sources active they will be in constant competition against each other to bias the input. 

The other thing to consider is the placement of the RC filters. I recommend placing the RC filter between the biasing portion of the schematic I outlined above and the input pins of the device - where R46, R47, R30, and R31 is. Due to passive tolerances, your RC filter cutoff frequency will naturally vary a small amount from channel to channel. By moving the RC filter in between the biasing portion of the circuit and the input pins of the device you effectively "close the loop" and the biasing portion of the circuit can correctly compensate for the passive differences of your RC filters.