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DAC3482: sometimes output is delayed

Part Number: DAC3482

Hello,

 

My customer is facing a strange behavior that output delay about 20us sometime.

The delay has been observed 1/10 ~ 1/100 times start-up. Their fifo sync configuration is as below.

config31 

Syncsel_mixer: 0100: SYNC

Syncsel_nco: 0100; SYNC

Syncsel_dataformatter: 00; FRAME

Sif_sync: 0

config32

Syncsel_fifioin: 0001; SYNC

Sysncsel_fifoout: 0001; SYNC

Clkdiv_sync_sel: 0; OSTR

 

Could you review these configuration and give your advice to their investigation?

 

Waveform is here

 

If you need other information, please let me know.

Best regards,

Katsu

 

  • Hi Katsu,

    You may refer to the app note below, section 2, for details on optimizing the FIFO.

    http://www.ti.com/lit/an/slaa584/slaa584.pdf

    Please check out the procedure to see if it can resolve the variation issue.

    -Kang

  • Hi Kang-san,

    thank you for your reply.

    20us is typo, actual 18~22ns.

    Do you have idea when make 22ns delay?

    if FIFO_OFFSET decrease 1 (4->3), the delay was observed frequently.

    Is there relation between fifio offset and the delay?

    Best regards,

    Katsu

  • Hi Katsu,

    You will have to find out the dataclk and dacclk rate in their system. 22ns must be one of the ratio of the clock running at 50MHz.

    Please review the document that I have send out. It talk about the reason for FIFO slippage and the exact clock rate for the FIFO. Since they are using dual sync mode, it is important to adjust the FIFO to optimize the delay.

    The difference in time delay between blue curve and red curve, are they between two different DAC3482 or two different channels of 1x DAC3482? The FIFO slippage will explain the situation of 2x DAC3482. If it is between two channels of DAC3482, then it is the setup/hold time of data with respect to DATACLK that need to be adjusted.

  • Hi Katsu,

    You will have to find out the dataclk and dacclk rate in their system. 22ns must be one of the ratio of the clock running at 50MHz.

    Please review the document that I have send out. It talk about the reason for FIFO slippage and the exact clock rate for the FIFO. Since they are using dual sync mode, it is important to adjust the FIFO to optimize the delay.

    The difference in time delay between blue curve and red curve, are they between two different DAC3482 or two different channels of 1x DAC3482? The FIFO slippage will explain the situation of 2x DAC3482. If it is between two channels of DAC3482, then it is the setup/hold time of data with respect to DATACLK that need to be adjusted.

  • Hi,

    sorry for slow response.

    Data clock is 100MHz and word mode, so the system doesn't have about 20ns clock. So I don't understand reason why output shifted about 20ns. Do you have any idea why 20ns slip?

    Blue curve is reference which uses the same input and clock, red is a device slipped output.

    best regards,

    Katsu

  • Hello Katsu-san,

    The FIFO slip on the sample is related to the FIFO_OUT_CLK. In word wide mode, it will be DACCLK/2/Interpolation or DATACLK/2. For 100MHz DATACLK, it will be 100MHz/2 = 50MHz

    Please see the plot with highlighted area. 

    Since you are using dual sync sources mode, the FIFO-offset need to be tuned to ensure optimized deterministic latency. 

    Please advise the delay variation is when compared between two DAC? If it is one DAC, then there should not be any concern for deterministic latency. If it is two DACs, then you will need to tune the FIFO offset to ensure deterministic latency. This is discussed in section 2.5 of the app note mentioned above.