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Part Number: ADS9224R
A customer of mine has some challenges with the ADS9224R. Kindly see their situation here. Direct questions are at the end of the post.
We are using a ADS9224R dual ADC in a zero-IF receive channel for RFID. We plan to have 25 of these receive channels interfacing to an FPGA. The ADC is intended to sample at its maximum sampling rate of 3Ms/s and we don’t want to use parallellisation of the serial data output data to be able to connect all channels to the FPGA. So we are running the serial data output at 60 MHz with a bus-width of one. We are using zone 2 datatransfer and retiming for the SPI interface (the STROBE is used as clock for the SPI data towards the FPGA)
With a 231kHz signal in the receive channel the IQ output from the ADC’s looks like the next plot:
In the plot we see discontinuities we don’t expect. These discontinuities disappear if we reduce the sampling rate to 1.5Ms/s and leave the serial data-rate at 60MHz as can be seen in the next plot:
We did check all signals in the SPI interface intensively:
From this and the fact that at 1.5Ms/s and 60MHz SPI interface, the signal looks ok, we conclude the datatransfer is OK and something is going wrong in the ADC conversion process.
We checked a lot of combinations of sample rate and SPI frequencies:
From the above we conclude the SPI data-rate doesn’t matter, but the sampling rate of the ADC does.
In the datasheet page 29 I found the following note:
This note, which we didn’t notice during the initial design, seems to suggest one needs to use at least 2 SDO’s in parallel and keep the data-transfer within 150ns, “for optimum performance”
This note might explain the problems we see, but it is not completely clear and leaves some questions unanswered.
Can you please give an answer to the following questions:
Thank you for posting your customer's question. I'll need to discuss this internally to understand the implications of this note.
Please allow a day or two for us to look into this.
Applications Engineer | Precision ADCs
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In reply to Ryan Andrews:
I'm checking some of the timing specifications for Clock Re-timer protocols. The customer is using CRT-S-SDR, correct? Can you please confirm whether they are using the internal or external clock to generate the STROBE output?
In the event that this is not related to an SPI read issue, we may need to look at the input circuitry for ADS9224R. The fact that slowing down the data rate improves the results could mean that the input voltage is not settling adequately between acquisitions. Is it possible to share a partial schematic showing the input driver stage?
I 'm the customer Obinna is referring to. So let me answer your questions directly.
We do indeed use CRT-S-SDR. To generate the STROBE output we use the external clock.
Attached are the schematic of the input stage of the ADS9224R as we currently use it and the schematic of the driving stage:
The capacitors C107, C109, C111 and C112 to ground are 330pF and are in line with the recommendation in the datasheet. However the TI application board does use an extra 3n3 differential capacitor between the inputs of the ADC. Do you think the problems we see could be related to our circuit not having the 3n3 capacitor ?
In reply to Bert Essink:
Today i modified the ADS9224R application board such that the input circuit matches our circuit. So i removed the 3n3 capacitor and changed the series resistor from 4.32 ohms to 560 ohms.
Now i see a similar effect on the application board :
The issue is in the input circuit, not in the datatransfer. Now we have to modify the input circuit such that we don't see the problem anymore.
Can you explain what is happening in the ADC that may cause this problem ?
Thanks for the update. I'm glad you were able to see the difference in performance immediately. I will work on a simulation to illustrate the input settling behavior that I was referring to.
Could you please edit your last post and reattach the image?
That simulation will be very helpful !!
I edited my previous post an reattached the picture. I hope it is ok now.
Please find the simulation results below. The important conclusion to observe is the difference in settling voltage error. This was measured by taking the difference between the DC steady-state voltage at the ADC input and the voltage across the sampling capacitors at the end of the acquisition phase (approx. 173 ns). Both circuits were tested with a DC input of -550 mV, which produced +3.905 V at the ADC input following the FDA stage. This equates to about -0.5 dBFS as near full-scale produces the worst-case settling. Your original circuit had a settling error of about -9.58 mV (about 77 LSBs). The EVM circuit had a settling error of about -20.382 uV (less than 1/2 LSB).
You can use the attached TINA-TI simulation file to see the difference. Clicking the "DC" button with the green circle will display the DC steady-state voltages at each meter. Use the value observed at "ADC_IN" to adjust the "Vin_ss" voltage source as needed before running Analysis -> Transient with different "VIN" voltages.
With the input you gave and the help of the simulation file you provided, we were able to modify the driver circuitry such that the settling error is close to what is achieved on the TI application board.
The discontinuities we saw are completely gone now.
Thanks a lot for your help with this issue !!
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