Part Number: ADS4449
in the datasheet there is a specification in the "OUTPUT TIMING" section for the values "tSU (Data setup time)" and "tH (Data hold time)". Note 9, however, says that these specificationy only apply with respect to the same channel output clock.
What I don't see is a specification of the maximum phase difference (or time delay) which can occur over temperatur between CLKOUTAB and CLKOUTCD. This is important for laying out the receiver-side clock domain crossings in the FPGA.
Let's assume that all traces on the PCB have exactly the same length, so we can ignore all board-level issues.
Can you help me with this?
I am checking with the design team to see if this information is available. Attached is some information we have sent other customers asking a similar question.
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In reply to jim s:
thank you for the document, it helps getting an understanding of how the datasheet is meant.
Have you had the chance to get some more data about the propagation delay between input clock and each of the data clocks? Maybe some information about temperature relationships?
This would help a lot!
In reply to Markus Haag:
The only other information I was able to obtain is show below.
Skew, from CD clock rise to AB clock rise(ns), measured at 250MSPS, is given in table below.
Other supplies (AVDD3V and AVDD) were kept at 3.3V and 1.9V respectively.
Thank you, that was exactly what I needed!
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