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ADS4449: ADS4449 Data-Clock output matching

Prodigy 70 points

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Part Number: ADS4449


in the datasheet there is a specification in the "OUTPUT TIMING" section for the values "tSU (Data setup time)" and "tH (Data hold time)". Note 9, however, says that these specificationy only apply with respect to the same channel output clock.

What I don't see is a specification of the maximum phase difference (or time delay) which can occur over temperatur between CLKOUTAB and CLKOUTCD. This is important for laying out the receiver-side clock domain crossings in the FPGA.

Let's assume that all traces on the PCB have exactly the same length, so we can ignore all board-level issues.

Can you help me with this?

Best Regards