This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • TI Thinks Resolved

ADS8668EVM-PDK: Master device must switch SPI mode (phase/polarity) in order to read command response data.

Prodigy 20 points

Replies: 2

Views: 60

Part Number: ADS8668EVM-PDK

Hello,

I am currently using the ADS8668EVM-PDK and have gone through the user's manual instruction to include the use of the built-in GUI that comes with the capture card (SDCC).  As of now, I am using the EVM board stand-alone and without the capture card.  When issuing a write command to the program register 03h Data: 41h, I am doing so in SPI Mode 1 (Low Polarity, Falling Edge) and based on the response of the ADS8668 it recognizes this command.  However, the expected response data which consists of the echoed data bits is returned in SPI Mode 0 (Low Polarity, Rising Edge).  With the return data having a phase shift, I decided to try the write command as SPI Mode 0 to then see how the response is read.  Doing this, the IC has no response, because it is expecting SPI Mode 1.  I have provided a screenshot of the results below...

Is it expected that the IC's response would be in SPI Mode 0?  There was an initial thought that maybe the IC was responding Asynchronously and arbitrary to the clock and therefore appeared to have a phase shift.  However, when playing with parameters and delaying the response bites, the IC still doesn't respond until the clock initiates.  Nonetheless, the data is still the same regardless of latency between the 16th and 17th clock pulses.  It doesn't make sense that you would issue a command in one SPI mode and then have to receive in a different one.  Any and all help is greatly appreciated!

Thank You,

Dustin

  • I apologize, I meant to include the following...

    GREEN: MISO

    PURPLE: MOSI

    BLUE: SCLK

    YELLOW: CS

    Thank You,

    Dustin

  • In reply to Dustin Lovell:

    Dustin,

    You are correct; mode 0 will work for capturing the SDO. The data transitions on the falling edge of the clock. Looking at the timing diagram you will notice the parameter tHT_CKDO (clock hold time to data out). This parameter indicates the minimum time after the falling edge that the SDO signal transitions (10ns).  See figure below.  So, this confirms that data transitions a short time after the falling edge as you noticed.

    I hope this helps, and sorry about your difficulties.

    Art Kay Senior Applications Engineer High Performance Linear

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.