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ADC08200: About the output level of ADC08200

Yatao Ling1
Expert 1840 points
Part Number: ADC08200

Hi TI expert,

Recently I choose ADC08200 to sample analog signals and outputs of 08200 are connected to an FPGA.

VA and VDR for 08200 are both set at +3.3V. Referring to 08200's datasheet in Page 6/29, its low level output is typically +0.4V when VA=VDR=+2.7V.

My FPGA is also powered by +3.3V. And the upper limit for '0' input for the FPGA is +0.8V.

I wonder since 08200 is powered by +3.3V, can its '0' output level fall below +0.8V and be recoginized correctly by the FPGA? (If '0' is +0.4V for VA=VDR=+2.7V, then perhaps '0' is +1V for VA=VDR=+3.3V?)

Regards

Yatao

  • 0
    TI__Genius 12780 points

    Hi Yatao,

    I don't think that the V_OL limit will exceed +0.8V when increasing from 2.7V to 3.3V V_DR . If the digital outputs scale, exactly one for one, with the V_DR increase, then 0.8V would be the absolute worst case for V_OL at 3.3V_DR.

    However, I believe the V_OL has more to do with headroom, so I would expect that the V_OL will not increase much at all. Hope this helps.

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Expert 1840 points

    Hi Dan,

    Thx for your answer.

    Then I'll use +3.3V to power the ADC.

    Regards

    Yatao