ADC08060: Clock Speed & Data reading

Hi William,

I believe the reason that operation is limited to 20MSPS is to guarantee data sheet performance specifications. My hunch is that the part will operate similarly in terms of conversions to output data at a slightly lower clock rate, but I cannot say for sure.

The output data bits (D0 - D7) are synchronous to the sample clock, but there is a delay (t_OD) between the edge of the sample clock and edge of the corresponding data bits. See timing diagram on page 17.

Best Regards,

Dan

I can't design in a part based on a hunch.  I have the same hunch, but I need a definitive yes or no, which is why I asked the question.