This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC3484: multiple DAC3484 output synchronization (phase alignment)

Part Number: DAC3484

Hello TI Support, 

I am using a FPGA board which drives two DAC3484 chip on the same board.  Each DAC3484 uses two channel output. Mixer is disabled. 

that is: DAC device 1, ch A and Ch C.

            DAC device 2, Ch A and Ch C. 

In total four(4) DAC channels being used, and we name it ch 1, ch 2 , ch3 and ch4. 

I am using the dual-sync source mode. I can basically get the two DAC output waveform "basically in sync", but still have some minor issues:

1). sometimes ch 1 and ch 2 are in sync; ch3 and ch4 are in sync. but ch1 and ch3 have 1~2 samples apart. 

2). sometimes ch2,3,4 are in sync, but channel 1 are out of sync. as shown in the picture below. 

I also enclosed the DAC3484 register dump before and after I set the DAC3484. 

Would you enlighten me what can be wrong in my setting here? my requirement is to get all four(4) channel(from two DAC devices) output waveform phase-aligned. 

Thank you. 

Mei Guodong

befor set DAC3484
reg # 0000 = 0000029c
reg # 0001 = 00000000
reg # 0002 = 00008082
reg # 0003 = 0000f001
reg # 0004 = 0000ffff
reg # 0005 = 00000260
reg # 0006 = 00003600
reg # 0007 = 00000000
reg # 0008 = 00000000
reg # 0009 = 00000000
reg # 000a = 00000000
reg # 000b = 00000000
reg # 000c = 00000000
reg # 000d = 00000000
reg # 000e = 00000000
reg # 000f = 00000000
reg # 0010 = 00000000
reg # 0011 = 00000000
reg # 0012 = 00000000
reg # 0013 = 00000000
reg # 0014 = 00000000
reg # 0015 = 00000000
reg # 0016 = 00000000
reg # 0017 = 00000000
reg # 0018 = 00000807
reg # 0019 = 00000454
reg # 001a = 00000020
reg # 001b = 00000800
reg # 001c = 00000000
reg # 001d = 00000000
reg # 001e = 00008888
reg # 001f = 0000ccc4
reg # 0020 = 00008801

reg # 0000 = 0000029c
reg # 0001 = 00000000
reg # 0002 = 00008082
reg # 0003 = 0000f001
reg # 0004 = 0000efff
reg # 0005 = 00000260
reg # 0006 = 00003600
reg # 0007 = 00000000
reg # 0008 = 00000000
reg # 0009 = 00000000
reg # 000a = 00000000
reg # 000b = 00000000
reg # 000c = 00000000
reg # 000d = 00000000
reg # 000e = 00000000
reg # 000f = 00000000
reg # 0010 = 00000000
reg # 0011 = 00000000
reg # 0012 = 00000000
reg # 0013 = 00000000
reg # 0014 = 00000000
reg # 0015 = 00000000
reg # 0016 = 00000000
reg # 0017 = 00000000
reg # 0018 = 00000807
reg # 0019 = 00000454
reg # 001a = 00000020
reg # 001b = 00000800
reg # 001c = 00000000
reg # 001d = 00000000
reg # 001e = 00008888
reg # 001f = 0000ccc4
reg # 0020 = 00008801

after configuration():
reg # 0000 = 0000029c
reg # 0001 = 00000000
reg # 0002 = 00008082
reg # 0003 = 0000f001
reg # 0004 = 0000ffff
reg # 0005 = 00000260
reg # 0006 = 00003600
reg # 0007 = 00000000
reg # 0008 = 00000000
reg # 0009 = 00000000
reg # 000a = 00000000
reg # 000b = 00000000
reg # 000c = 00000000
reg # 000d = 00000000
reg # 000e = 00000000
reg # 000f = 00000000
reg # 0010 = 00000000
reg # 0011 = 00000000
reg # 0012 = 00000000
reg # 0013 = 00000000
reg # 0014 = 00000000
reg # 0015 = 00000000
reg # 0016 = 00000000
reg # 0017 = 00000000
reg # 0018 = 00000807
reg # 0019 = 00000454
reg # 001a = 00000020
reg # 001b = 00000800
reg # 001c = 00000000
reg # 001d = 00000000
reg # 001e = 00004444
reg # 001f = 00004424
reg # 0020 = 00001401

reg # 0000 = 0000029c
reg # 0001 = 00000000
reg # 0002 = 00008082
reg # 0003 = 0000f001
reg # 0004 = 0000efff
reg # 0005 = 00000260
reg # 0006 = 00003600
reg # 0007 = 00000000
reg # 0008 = 00000000
reg # 0009 = 00000000
reg # 000a = 00000000
reg # 000b = 00000000
reg # 000c = 00000000
reg # 000d = 00000000
reg # 000e = 00000000
reg # 000f = 00000000
reg # 0010 = 00000000
reg # 0011 = 00000000
reg # 0012 = 00000000
reg # 0013 = 00000000
reg # 0014 = 00000000
reg # 0015 = 00000000
reg # 0016 = 00000000
reg # 0017 = 00000000
reg # 0018 = 00000807
reg # 0019 = 00000454
reg # 001a = 00000020
reg # 001b = 00000800
reg # 001c = 00000000
reg # 001d = 00000000
reg # 001e = 00004444
reg # 001f = 00004424
reg # 0020 = 00001401

  • Hello,

    You may refer to attached app note for detail. Most likely you will need to re-adjust the FIFO based on empirical data. See section 2.5 particularly. 

    http://www.ti.com/lit/an/slaa584/slaa584.pdf

    -Kang

  • Hello Kang, 

    Thank you for your reply. 

    I read through your appnote (slaa584.pdf), and it is quite helpful in understanding the dual sync mode.

    I tried adjusted my register settings, but the issue persists. the issue now is:

    1). sometimes ch 1 and 2 are in sync; ch3 and 4 are in sync, but ch 1 and ch3 may be offset by 2 data samples. 

    2). sometimes ch 1,2,3 are in sync(phase-aligned), but channel 4 are out of sync by 1~2 samples.

    3). sometimes ch 3,4 are in sync, but channel 1 and 2 are offset by up to 6 samples. (see enclosed picture)

    I also enclosed my register dump here before and after setting the DAC3484. Would you please give me any advice any setting wrong here? 

    befor set DAC3484
    reg # 0000 = 0000029c
    reg # 0001 = 00000000
    reg # 0002 = 00008082
    reg # 0003 = 0000f000
    reg # 0004 = 0000fffe
    reg # 0005 = 00000260
    reg # 0006 = 00003a00
    reg # 0007 = 00000000
    reg # 0008 = 00000000
    reg # 0009 = 00000000
    reg # 000a = 00000000
    reg # 000b = 00000000
    reg # 000c = 00000000
    reg # 000d = 00000000
    reg # 000e = 00000000
    reg # 000f = 00000000
    reg # 0010 = 00000000
    reg # 0011 = 00000000
    reg # 0012 = 00000000
    reg # 0013 = 00000000
    reg # 0014 = 00000000
    reg # 0015 = 00000000
    reg # 0016 = 00000000
    reg # 0017 = 00000000
    reg # 0018 = 00000807
    reg # 0019 = 00000454
    reg # 001a = 00000020
    reg # 001b = 00000800
    reg # 001c = 00000000
    reg # 001d = 00000000
    reg # 001e = 00008888
    reg # 001f = 0000ccc4
    reg # 0020 = 00008801

    reg # 0000 = 0000029c
    reg # 0001 = 00000000
    reg # 0002 = 00008082
    reg # 0003 = 0000f000
    reg # 0004 = 0000efff
    reg # 0005 = 00000260
    reg # 0006 = 00003600
    reg # 0007 = 00000000
    reg # 0008 = 00000000
    reg # 0009 = 00000000
    reg # 000a = 00000000
    reg # 000b = 00000000
    reg # 000c = 00000000
    reg # 000d = 00000000
    reg # 000e = 00000000
    reg # 000f = 00000000
    reg # 0010 = 00000000
    reg # 0011 = 00000000
    reg # 0012 = 00000000
    reg # 0013 = 00000000
    reg # 0014 = 00000000
    reg # 0015 = 00000000
    reg # 0016 = 00000000
    reg # 0017 = 00000000
    reg # 0018 = 00000807
    reg # 0019 = 00000454
    reg # 001a = 00000020
    reg # 001b = 00000800
    reg # 001c = 00000000
    reg # 001d = 00000000
    reg # 001e = 00008888
    reg # 001f = 0000ccc4
    reg # 0020 = 00008801

    after configuration():
    reg # 0000 = 00000298
    reg # 0001 = 00000000
    reg # 0002 = 00008082
    reg # 0003 = 0000f000
    reg # 0004 = 0000fffe
    reg # 0005 = 00000260
    reg # 0006 = 00003a00
    reg # 0007 = 00000000
    reg # 0008 = 00000000
    reg # 0009 = 00000000
    reg # 000a = 00000000
    reg # 000b = 00000000
    reg # 000c = 00000000
    reg # 000d = 00000000
    reg # 000e = 00000000
    reg # 000f = 00000000
    reg # 0010 = 00000000
    reg # 0011 = 00000000
    reg # 0012 = 00000000
    reg # 0013 = 00000000
    reg # 0014 = 00000000
    reg # 0015 = 00000000
    reg # 0016 = 00000000
    reg # 0017 = 00000000
    reg # 0018 = 00000807
    reg # 0019 = 00000454
    reg # 001a = 00000020
    reg # 001b = 00000800
    reg # 001c = 00000000
    reg # 001d = 00000000
    reg # 001e = 00004444
    reg # 001f = 00004424
    reg # 0020 = 00001401

    reg # 0000 = 00000298
    reg # 0001 = 00000000
    reg # 0002 = 00008082
    reg # 0003 = 0000f000
    reg # 0004 = 0000efff
    reg # 0005 = 00000260
    reg # 0006 = 00003600
    reg # 0007 = 00000000
    reg # 0008 = 00000000
    reg # 0009 = 00000000
    reg # 000a = 00000000
    reg # 000b = 00000000
    reg # 000c = 00000000
    reg # 000d = 00000000
    reg # 000e = 00000000
    reg # 000f = 00000000
    reg # 0010 = 00000000
    reg # 0011 = 00000000
    reg # 0012 = 00000000
    reg # 0013 = 00000000
    reg # 0014 = 00000000
    reg # 0015 = 00000000
    reg # 0016 = 00000000
    reg # 0017 = 00000000
    reg # 0018 = 00000807
    reg # 0019 = 00000454
    reg # 001a = 00000020
    reg # 001b = 00000800
    reg # 001c = 00000000
    reg # 001d = 00000000
    reg # 001e = 00004444
    reg # 001f = 00004424
    reg # 0020 = 00001401

  • Hello Kang, 

    1).As per your appnote start up sequence, the data will fill into the FIFO first, then reset the Read Pointer through OSTR. after which the TX_ENABLE is set to High in order to output waveforms. 

    I have two DAC chip, hence need to set the TX_ENABLE respectively to each DAC chip one by one through software. from this perspective, will it cause the DAC output waveform phase offset? 

    2). I implement the events sequence this way:

    (a): reset WP;

    (b): set TX_Enable to high.

    (c): open Gate to write data into DAC FIFO.

    (d): 2 clocks after opening date in (c), OSTR becomes high to start read data.

    Because the Gate and OSTR is a global signal which is set to High simultaneously to both DAC chip, should the two DAC output waveform in synchronization? (but the test results are they often offset by 2 clocks). 

    3). as described in 2). my test results are most of the time the offset is 2 data samples, sometimes it can be up to 6 data samples. I am not sure if this is because the FIFO depth is 8 samples so one channel is delayed by one complete 8 samples? but how could this happen since my GATE and OSTR are given simultaneously ? 

    Thank you.

    Mei Guodong

     

  • Hi

    By design without additional care, the channels within 1x DAC3484 device will be synchronized. The fact that you are not seeing consistent output phase on even one DAC device indicates that your input pattern from the FPGA is not source synchronous. I do not think this is a DAC issue. Please double check on your FPGA, or even send out constant patterns to check the alignment on the data source.

    Please also clarify which channel is which device. I would like you to first focus on getting stable synchronized channel on the two channels of 1 device, and then another two channels of another device. You may then proceed with synchronization of two devices.

    -Kang

  • Hi Kang, 

    Thanks for your reply. 

    I should update you today after giving proper SYNC signal to each DAC device, I am able to get DAC 1 (ch1 and ch2) in sync. the waveform overlap perfect. 

    DAC 2(ch3 and ch4) also overlap. (please see below plots). 

    However, there is an offset of 2 samples between ch1 and ch3 most of the times; sometimes it becomes 6 samples. 

    Please would you advise what can be the reasons why they jump between 2 samples and 6 samples? I will appreciate if you can advice on my questions in previous post. Thank you. 

  • Hi

    guodong mei said:

    1).As per your appnote start up sequence, the data will fill into the FIFO first, then reset the Read Pointer through OSTR. after which the TX_ENABLE is set to High in order to output waveforms. 

    I have two DAC chip, hence need to set the TX_ENABLE respectively to each DAC chip one by one through software. from this perspective, will it cause the DAC output waveform phase offset? 

    TX_ENABLE is asynchronous to the FIFO and ISTR/FRAME/OSTR. It only enabled the DAC core. The latency of the device is completely controlled by ISTR/FRAME/SYNC/OSTR

    guodong mei said:
    (c): open Gate to write data into DAC FIFO.

    I am not sure what you mean by GATE. If you are gating input data, then you may have some problems. The assumption is that you are aligning data at the input side also with ISTR/FRAME/SYNC signal

    guodong mei said:
    3). as described in 2). my test results are most of the time the offset is 2 data samples, sometimes it can be up to 6 data samples. I am not sure if this is because the FIFO depth is 8 samples so one channel is delayed by one complete 8 samples? but how could this happen since my GATE and OSTR are given simultaneously ? 

    how are you controlling the ISTR/FRAME/SYNC? You will need to control both the input FIFO pointer reset and output FIFO pointer reset to ensure deterministic latency.

    -Kang

  • Hi,

    I will be closing this thread for now as I haven't heard back from you. You may always come back and reply to re-open the thread again. Good luck.

    -Kang

  • Hi Kang, 

    I was checking with hardware board designer regarding your questions hence this reply was delayed. 

    Though I am still finding out the details on ISTR/FRAME signal in hardware design yet, I am using SYNC signal as sync src for WP reset. 

    The GATE signal in my email is a active High signal, when enabled, the data starts to flow into DAC3484. 

    My flow of control is this: 

    1). I set a SYNC signal to reset WP pointer.

    2). after 20 us, enable Gate in order to let data flow into the DAC3484 FIFO.

    3). 2 clocks after GATE signal, the OSTR signal is give to re-set the RP pointer.

    4). pull the TX_Enable to High for waveform output. 

    Is there any issues in this sequence? 

    quoting your notes: "The assumption is that you are aligning data at the input side also with ISTR/FRAME/SYNC signal"

    Does it mean when data starts flow in, I should also set the SYNC signal simultaneously in order to reset the WP pointer? 

    Does the SYNC and OSTR signal need to be a "pulse signal"? or can it be a permanent High signal to reset the WP/RP? 

    Thank you. 

    Mei Guodong

  • Guodong,

    The main problem I see is that the SYNC signal is not synchronously aligned with the Gate control. You just have a generic 20us delay. One requirement, as highlighted in the app note, is that the input data must be aligned with the SYNC input. This is assuming the input data is also loaded synchronously. Please double check. 

    -Kang