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DDC316: Data on DOUTx are shifted out on rising edge of DCLK, why?

Bernhard Gaus
Prodigy 50 points
Part Number: DDC316

Data on DOUTx are shifted out on rising edge of DCLK but on page 17 the datasheet states "Data are shifted out on the falling edge of DCLK." and the timing diagram "Figure 1. Serial Interface Timing" on page 6 also.

But when I measure the signals directly at the DDC316 with a logic analyser the traces show me that data on DOUTx are shifted out on the falling edge of DCLK (e.g. see cursor A).

What's going on there?

  • 0
    TI__Mastermind 49176 points

    Hello Bernard,

    Based on the datasheet, the data is shifted out on the falling edge of DCLK and additionally, there is a propagation delay from the falling edge of DCLK to DOUT (max of 21ns). Let us say, if we assume that the Data on DOUT is shifted out on the rising edge of DCLK, then the data edge to the right of cursor A seems to violate tDOHD and no tDOPD as mentioned in the datasheet.

    From your timing, the DCLK frequency is not evident. Are you running the DCLK at 25ns period? Can you slow down the DCLK to check the data edges w.r.t DCLK?