ADS54J69: minimum device clock frequency

In the parametric selection for the ADC, the max sample rate is specified as being 500Msps but no miimum is listed. I was assuming that the device clock frequency could be used upto 1GHz when the decimation by 2 was applied otherwise upto 500MHz. Looking at the "Recomended Operating Conditions" section 7.3 of the datasheet however, we see that the system clock is defined with a minimum frequency of 500MHz. Is this actualy the minium input frequency or the minimum to acheive 500Msps? For example, if I wanted to use an external clock of say 300MHz, would this be allowed giving me an effective sample rate of 150/300 depending on the decimation setting? Looking at equivalent devices and DACs etc the device clock maximum is normally only listed or a significantly lower minimum. 500MHz to 1GHz seems to be quite restricted. many thanks.