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DAC60508: no CS_ toggling is required at synchronous mode?

Kazuhiko Hirano
Genius 11613 points
Part Number: DAC60508

Hello,

 

My customer uses one DAC60508 and a host communicates only the DAC60508 via SPI.

So the SPI interface is not shared with other device.

And they do not use asynchronous update, only use synchronous mode.

 

In this case, can they keep CS_ always low by connecting CS_ pin to GND?

 

Best regards,

 

K.Hirano

  • 0
    TI__Mastermind 46290 points

    Hirano-san,

    Regardless of if the device is operated in synchronous or asynchronous update modes concerning the behavior of the LDAC functionality, the CS signal is required. As explained on page 25 of the datasheet, the rising edge of CS is what triggers the latching mechanism of the SPI interface (i.e. for all registers, not just DAC data). I have pasted the relevant section below for convenience.

    The access cycle ends when the CS pin is de-asserted high. If the access cycle contains less than the minimum clock edges, the communication is ignored. If the access cycle contains more than the minimum clock edges, only the last 24 or 32 bits are used by the device.