• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 47 subscribers
  • Views 365 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC3421: Test patterns

Daniel Baldor
Intellectual 310 points
Part Number: ADC3421

Hi,

I am working on interfacing the ADC3421 to my FPGA using single serial link (1 per output).  The ADC is running at 25MSPS and I have had some trouble getting the correct output out of all the different test patterns.  I am finding the sine output has different outputs than those stated on the datasheet (though still looks like sine if you plot it) and the ramp function take 4 samples to increment 1 value.  Would you be able send me a capture of the serial outputs with resultant values for the both of these test patterns?  I find that the static values seem to work correctly (eg alternating between 0x555 and 0xAAA).

Thanks

  • 0
    TI__Guru* 91947 points

    Daniel,

    We are looking into this.

    Regards,

    Jim

  • 0
    TI__Genius 12780 points

    Hi Daniel,

    For the ramp, are the values incrementing from 0 to 4095? For the sinewave, what values are you seeing?

    Due to work limitations right now, it may difficult to provide the test pattern results that you have requested.

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Intellectual 310 points

    The ramp output increments 1 lsb every 4 samples - here is an example (unsigned decimal): 1143,1143,1143,1143,1144,1144,1144,1144,1145... (pattern continues)

    For the sinewave I get the following values (unsigned decimal in order): 1384, 978,0,3117, 2711,3117,0,978  (pattern repeats)

    I verified this at two sampling speeds 25MHz (max of the part) and 12.5MHz. just to rule out any timing issues in my fpga design.  The interface to the adc outputs is 1 wire mode (not sure if that is relevant or not).  When I use custom pattern mode the data comes out correctly all the time.

  • 0 in reply to Daniel Baldor
    TI__Genius 12780 points

    Hi Daniel,

    The ramp test pattern changing on every 4th sample is an issue with the test pattern itself. Unfortunately, we do not have a fix for this.

    Additionally, I think the 8 point sine wave values in the datasheet are not correct. Here are some data captures with the sinewave test patter.

    ADC3424 Test Pattern.pptx

    After I verify on the ADC3421EVM, these items will be corrected in the next datasheet revision.

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Intellectual 310 points

    Hi Dan,

    Thanks for the update.  One more thing that was not indicated on the datasheet as far as I can tell was the setup and hold time for the FCLKP and FCLKM signals.  I used the values for the adc data pins but I am not sure if that was correct or not.

    Thanks

  • 0 in reply to Daniel Baldor
    TI__Genius 12780 points

    Hi Daniel,

    Yes, please use the setup and hold time that is used for the data signals.

    Best Regards,

    Dan