Other Parts Discussed in Thread: ADS54J69
Hello
I have been over several posts and datsheet of the similar devices and I am a little bit lost:
I am using the ADS54J69 in 4222 configuration with an arria10 Altera/intel FPGA.
In the FPGA I implemented the Altera JESD204b IP.
If I do NOT select "byte and bit reversal" meaning the IP assumes that it receives lowest bit form lowest byte first, on aspecific lanes
I managed to get a "link-up" and received data.
However while reading again the datasheet it seems to me that the ADS54J69 sends the highest bits of the highest bytes first. If I check the option in the FPGA to inform the FPGA it shall expect first the highest bit of the highest byte, I did not manage to get a link-up. The IP still asserts the sync signal.
Unfortunately I did not manage to open the FPGA refernce design of the eval platform. It seems that with Quartus 18.1 this does not work straight.
If by change you have a configuration file for this 4222 mode of this device it would also help me alot and save quite some times on my side.
Thanks
Nicolas