This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS54J60: ADS54J69

Part Number: ADS54J60
Other Parts Discussed in Thread: ADS54J69

Hello
I have been over several posts and datsheet of the similar devices and I am a little bit lost:

I am using the ADS54J69 in 4222 configuration with an arria10 Altera/intel FPGA.

In the FPGA I implemented the Altera JESD204b IP.

If I do NOT select "byte and bit reversal" meaning the IP assumes that it receives lowest bit form lowest byte first, on aspecific lanes

I managed to get a "link-up" and received data.

However while reading again the datasheet it seems to me that the ADS54J69 sends the highest bits of the highest bytes first. If I check the option in the FPGA to inform the FPGA it shall expect first the highest bit of the highest byte, I did not manage to get a link-up. The IP still asserts the sync signal.

Unfortunately I did not manage to open the FPGA refernce design of the eval platform. It seems that with Quartus 18.1 this does not work straight.

If by change you have a configuration file for this 4222 mode of this device it would also help me alot and save quite some times on my side.

Thanks

Nicolas

  • ADS54J69_2x_dec_lowpass_4222.cfgNicolas,

    The data should come out per the data sheet. Please try the attached configuration file for the 4222 mode. Make sure to issue a hard reset after the clocks are present to the ADC but before programming the registers. The link will get established if you reverse the bytes as the K28.5 characters are 0xBCBC.

    Regards,

    Jim

  • Hi Jim

    Thanks for your quick reply.
    I will try your configuration script.
    I am sorry to insist but I would like to be absolutly sure, 

    on a specific lane (for a 4222 configuration) We got the highest of the sample and then the other down to the lowest bit. Meaning we receive bit 15 then 14,...until 0.
    I insist since the data I have for the moment do not make sense and I am looking for any tracks which may explain my issue.

    Thanks

    Nicolas

  • Hello

    The last access of your configuration file for the ADC , which page does it target?

    I did not manage to match it with a register in the datasheet.

    Regards

    Nicolas

  • Nicolas,

    The data sheet will be updated in the future to include this. Please download the latest version of the ADC54J60 data sheet as this one has been updated. The only difference between the two parts is the ADS54J69 does not offer the bypass option. For the most part, the register map is identical for the two.

    Regards,

    Jim

       

  • Jim

    Sorry to insist but may I ask you to clarify which bit is sent out first, is it bit(15), or bit(8), or bit(7) or bit(0)?

    My understanding is that it should be the bit (15) but I would like to be absolutely sure

    Thanks

    nicolas

  • Nicolas,

    If the Device sends MSB byte first in SERDES Lanes. Then the JESD IP output data is expected to be MSB first from the octets.

     

    Bit 15 first in the Octet 0 , Bit 7 first in the Octet 1 and so on…

     

    Regards,

     

    Jim