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Part Number: ADS7945
Looking at the DEVICE OPERATION of 16-clock mode in the datasheet, SDO is kept LOW durind 15 and 16 cycle of SCLK. However, customer found that SDO is pulled HIGH at 16 cycle of SCLK. Is this a correct behavior?
SDO was sometimes kept LOW at 15 and 16 cycle of SCLK like datasheet. But, sometimes, customer find above behavior. Could you make sure if this is expected behavior?
This is correct behavior.
When CS is held low past the 16 SCLK, the device continues to output recently converted data starting with the 16 SCLK falling edge.
In the first image, note that the beginning two bits are 1 0. After the 16 SCLK, then the data is being outputted again. At the 17 and 18 bit (CS brought high) is now repeating 1 0 again. That is why 17 is high, and then SDO quickly goes low at the next clock change. But once CS is brought high, SDO goes to tri state.
In the second image, note that the beginning two bits are 1 1. After the 16 SCLK, then the data is being outputted again. which means bit 17 and 18 are also high. this is why the second image does not have low state when CS is brought high.
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In reply to Cynthia:
Thank you for clear explanation. I and customer understood your answer.
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