Hi team,
Looking at the DEVICE OPERATION of 16-clock mode in the datasheet, SDO is kept LOW durind 15 and 16 cycle of SCLK. However, customer found that SDO is pulled HIGH at 16 cycle of SCLK. Is this a correct behavior?
SDO was sometimes kept LOW at 15 and 16 cycle of SCLK like datasheet. But, sometimes, customer find above behavior. Could you make sure if this is expected behavior?
Regards,
Saito