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ADS8900BEVM-PDK: How can I configure the PHI for 3.3V digital logic?

Erik Anderson41
Intellectual 915 points
Part Number: ADS8900BEVM-PDK

Per EVK documentation, it says that its configured for 3.3V in some places, other places it says the PHI can be configured for 3.3V logic.  But by default it seems the EVK has DVDD = 1.8V and the SPI signals are all 1.8V.  

I would like to use the EVK with 3.3V logic, but there are no instructions on how to achieve this.  Can you walk me through how to change it?

Thanks,

Erik

  • 0
    Intellectual 915 points

    Are you around today and can answer this one?  I'm a bit pressed on time.  thanks.

  • 0 in reply to Erik Anderson41
    TI__Mastermind 36240 points

    Hello Erik,

    Unfortunately, there is no way to adjust the operating DVDD voltage on the EVM.  However, if you are interfacing the EVM with your own host MCU without the PHI board connected, you can supply the EVM_DVDD with any valid voltage from 2.3V to 5.5V.

    If using the on-board LDO to power the analog, you can also provide a +5.5V supply to EVM_REG_5V5 (again, without the PHI board connected).   EVM_ID_PWR can be left floating since this only powers the  board ID EEPROM.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Intellectual 915 points

    Thanks Keith, we decided to just get the FPGA up and running and start to look at ADC output.

    Can you look at our timing and see if it looks okay to you?  We've tied CS and CONVST together.  We are using dual SPI, zone 2.  16.7MHz clock.  As far as I can tell, we are OK.  We made sure to not have any clock edges during the quiet acquisition / conversion times when CS goes high.  And CS to SCLK timing looks like there's plenty of margin.

    EDIT: I do have one question.  We were looking at RVS but it never goes high.  I think this is because we have tied CS and CONVST together, right?  So, when CS goes high a new conversion starts, therefore RVS would never go high to indicate conversion done.  This is fine as we are not planning to use it, but just observed this and wanted to make sure my understanding is correct.

    Thanks!

    Erik

  • 0 in reply to Erik Anderson41
    TI__Mastermind 36240 points

    Hello Erik,

    At first pass, your timing looks correct.  For the quiet periods, it looks like you have 1 SCLK, or 60nS, which is plenty of time.

    Also, RVS should stay low based on your timing diagram and the fact that /CS and CONVST are connected together.

    If you kept /CS high long enough, you should see RVS transition high at the end of the conversion period.  This would be useful if you wanted to read data in Zone 1, for example.  In your case, /CS is only high for about 240nS, which is less than the 600nS minimum period for the conversion to take place.

    Regards,
    Keith