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ADS54J60EVM: ADS54J60EVM

Part Number: ADS54J60EVM
Other Parts Discussed in Thread: ADS54J60, TSW54J60EVM, LMH5401

HI,

I have the evaluation board of of the ADS54J60 (these are actually 2 boards: one is with the A2D, the other is with the FPGA).

1. I want to test the BER of the ADC using the "ADS54Jxx GUI v1.6" and the "High Speed data converters Pro" programs.

I did not find how to do it. I saw an option to enable the test pattern but did not see any option to verify if all the data arrived correctly to the FPGA or not. I did not find a way to count BER errors.  How it can be done?

2. I saw that in the "High Speed data converters Pro" program, in the "instrument option" tab, under "SERDES test options" there is a way took at the eye and at the side there is a color BER bar. According the color it is hard to say if i had BER errors or not. Is there a way to read the BER counter and not to rely on the bar colors?

Thanks,

Yuval

  • Yuval,

    BER was implemented only to a few specific devices, as it requires special data packing to be handled in the firmware. I do not believe we had a firmware build for this part. We are looking into this.

    What LMFS setting are you using and at what ADC sample rate?

    Regards,

    Jim

  • Hi,

    I am following the instructions in SLAU629A so the sample rate is 983.04M.

    I try 3 types of LMFS: 8224, 4244 and 4211

    Yuval

  • Yuval,

    There is a chance we may have something that works (4211 mode) for you as is. Please follow the instructions below that were provided by our software development team.

     

    1.       Make sure the “Devices and File Info.ini” file is edited under the TSW14J56RevD folder. This file is located at the following location:

    “C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J56revD Details\Device and File Info.ini”. In this file you need to  remove the comment “CER Validate Error Count” under the ADC section.

     

    2.  Copy the provided ADS54J60_LMF_4211_CER.ini to the following location:

    “C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J56revD\ADC files”.

     

     

    3.      The  Input Sine Tone, ADC Sampling clock and FPGA Reference clock must all be synchronized.

     

    4.       The Input Sine Frequency (Fin), ADC sampling Frequency (Fs) and Number of samples per clock(N) (entered in HSDC pro GUI) must be in an relation, such that each cycle taken in CER test iteration must contain discrete number of samples which will be repetitive in successive cycle (refer point 5).

    We have a “coherent frequency calculator” utility to compute the input sine wave frequency (Fin) in relation to Fs and N. The utility can be found in the Coherent Frequency Calculator folder attached.

     

    5.       All CER testing related information are added in the attached file called “HSDC Pro FAQ & Troubleshooting Guide.docx”.

     

    Refer the Section “How to Measure Code Error Rate (CER) in TSW14J57(applicable to J56 also)

    The steps to use the calculator utility will be explained in under “Using Coherent Frequency Calculatorsubdivision. The relation between Fs, Fin and N is explained in “overview” subdivision.

     

    6.       The No. of samples per cycle (N) in HSDC pro GUI has a range minimum of 2^ADC_resolution maximum of 131072 samples and it must be multiple of 4 for this mode.

    Regards,

    Jim

    CER.zip

  • HI,

    1. I could not open the file "Device and File Info.ini". When i tried to open with notepad++, i got unreadable signs. What am i doing wrong?

    2. My eval board has the J60 device. I hoe that your instructions work for J60 also.

    Thanks,

    Yuval

  • Device and File Info.iniYuval,

    See if you can replace your copy of the Device and File Info.ini with the one attached. This one has the changes made. I was able to open this file using notepad. Not sure why you are having issues with this. I have not had a chance to test this but it should work for the ADS54J60 device.

    Regards,

    Jim

  • Thanks, I got the file and even could open it.

    Regarding the parameter (CER Validate Error Count) that you asked me to remove its comment, i did not see it under the ADC section as you said but under the DAC section. Is it OK?

    [ADC]
    Menu Disable = "Number of Channels;OnBoard Diagnostics;CER Testing;IO Delay;JESD204B Error Injection"
    Disable Controls = Pattern Verifier;TSW14J56 TRANSMITTER;CONFIG;IO Delay;Calibrate-Individual Lane Info;Debug Features"

    [DAC]
    Menu Disable = "Cursor Lock;2 Channel Display;Save Raw ADC Codes as Binary File;Import Binary File;Import Data File;Notch frequency bins;Capture Option;Number of Channels;dBFs;Analysis Window Markers;Other Frequency Options;User Profiles;NSD Marker;OnBoard Diagnostics;CER Testing;Phase Plot;Phase in Degree;IO Delay;JESD204B Error Injection"
    Disable Controls = "CER Validate Error Count;Pattern Verifier;Delay in µs;Number of Triggers;Arm On Next Capture;Info"

  • I did the edit for you already. The parameter can stay in the DAC section as you are not using a DAC.

  • HI,

    I tried today to run the CER test but without success.

    here is what i did (please tell me what did i make wrong):

    ADS54J60 GUI Configuration

    1. Configured the clock to 983.04MHz

    2. Programmed the "ADS54J60_LMF_4211.cfg " file

     

    HSDC Pro GUI Configuration

    3. selected in the ADC drop-down menu the file ADS54J60_LMF_4211_CER (as a sequence it downloaded the FW automatically)

    4. Entered 983.04M in the ADC Output Data Rate field

    5. Reset the board and did one capture (works fine)

     

    Run CER TEST

    6. I connected a 120KHz sine wave to input A of the ADC (I tried both 1dBm and 10dBm).

    7. I inserted 8192 into the “No. of sample per cycle” field

    8. In the “Threshold” field I inserted the number 100 (i did it only to threshold #1). Is it correct? how do you define this number? BTW, why there are 5 thresholds?

    9. Pressed the start button.

     

    I got many failures. What did i do wrong?

    BTW, Is there a way to reset the counters without closing the program ?

     

    Yuval

  • Yuval,

    See attached for more help with this testing.

    Regards,

    Jim

    CER Testing Help.docx

  • HI Jim,

    Thanks for your support.

    Unfortunately it still does not work.

    This is what I did:

    1. I configured the boards with the ADS54J60_LMF_4211_CER and verified that i can grab a sine wave.

    2. I entered the CER testing window and in the "No of sample per cycle" I entered the number 81920.

    3. I configured the signal generator to 132K, 10dBm

    4. I entered at threshold 1 the value 100 and press the start test.

    5. The error counter constantly increased.

    6. The weird thing is that i tried to increment the value of the threshold but it did not help. I even entered the value 70000 which must give you zero errors but the error counter still increments.

    Please tell me what am i doing wrong.

    Thanks,

    Yuval 

  • Yuval,

    You must have a coherent input. How are you creating this signal?

    Regards,

    Jim

  • Yuval,

    It appears the ADC must be offset binary mode for this to work. We just tested this successfully on our setup. Please use the two files attached 9one is for setting up the ADC, the other is an updated .ini for HSDC Pro).

    Regards,

    Jim

    ADS54J60_LMF_4211_offset_binary.cfgCER observation.pptxADS54J60_LMF_4211_CER _offset_binary.ini

  • 6811.ADS54J60_LMF_4211_CER _offset_binary.ini3005.CER observation.pptx4572.ADS54J60_LMF_4211_offset_binary.cfgYuval,

    We found out that the ADC must send data using offset binary format for this to work. We tested this successfully with our setup. Please try with the attached files. One file is to configure the ADC for offset binary mode, one file is an updated .ini file needed by HSDC Pro GUI, and the other file is our test results.

    Regards,

    Jim

  • HI,

    Thanks for your answer, now it works much better but still not perfect.

    I have few questions:

    1. What type of generator do you use to generate the input signal. I am using a ROHDE&SCHWARZ SML01 generator to create the input signal. I am asking this because i see that my thresholds are much higher than yours. I saw that when you you entered a 100 threshold you got 0 error. In my case, even with a 1000 threshold, i see few errors. The difference is that I run it endless while you ran it 6000 cycles. Still i would expect that at this low frequency a 1000 threshold will be enough.

    2. The number of the threshold is in LSB units, right?

    3. Do you have a way to test the BER of the digital interface only? This way i can test bit exact and should get 0 errors.

    Thanks,

    Yuval

  • Yuval,

    1. We use a HP8643A. The 10MHz reference output from this generator is connected to J6 on the ADC EVM to synchronize the LMK with the signal generator. Both PLL Lock LED's need to be illuminated on the ADC EVM, indicating the LMK is locked to the signal generator reference.

    2. I am checking on this.

    3. We do not have the required firmware or software to support BER testing of this device.

    Regards,

    Jim

  • HI,

    I connected the signal generator 10MHz reference to the ADC EVM and the results are much better than before.

    Still, i do not get the results you get.which is zero errors at 100 threshold.

    In my test, i see errors at even 500 threshold.

    I see that your test stopped after 6K cycles. Did you try to run it endlessly and verify no failures after let's say 15 minutes?

    Yuval

  • Yuval,

    I did run for 30 minutes and the results are attached. You will notice I am getting many more errors now. What did you set the No. of samples per cycle on your run? Was your tone the same frequency that I am using?

    Regards,

    Jim

    30 minute run.pptx

  • I am using the same configuration you do. Fin = 276K, No of samples 81920, Level = 10dBm.

    BTW, my results are much worse than yours. According your attached file, threshold = 300 gives you no errors. In my case i need to set the threshold to a much bigger number and i never got no errors when the test ran for a long time.

    I left it running over night and at this case, i got errors even at threshold of 1800.

    I do not know how your algorithm works but i see that the error counter does not increment one by one. In a sudden I see many errors (depends on the threshold level)

    Yuval

  • and one more thing.

    I noticed that sometimes the tests are more stable than the the others. I mean that in some tests the error counter increments immediately and in other tests it takes some time until it starts to increment and also in this case the increment is slower.

    Yuval

  • Yuval,

    In HSDC pro GUI, got to the data capture options tab then select capture options. Change the default capture size to 131072. Go back to the main menu then enable the auto calculation of coherent frequencies and enter 131072 for the analysis window samples. Next enter 277.5k in the ADC input target frequency and set your sig gen to this value. Click on capture. You should see a coherent frequency overlaying the actual frequency when displaying codes. See file attached. Run the CER test and see if your are getting similar results. If not, please send a screen shot of both views.

    Regards,

    Jim

    Coherent Input.pptx

  • Yuval,

    Make sure you can get this working with no errors using the long transport test pattern. Use 81920 samples for this test. To enable this, set bit 4 to "1" in address 0x00 of page 0x6900.

    Regards,

    Jim  

  • HI,

    Still does not work

    1. I do not see the red line as you see it in the graph

    2. I did everything you told. At first it looks like it works, but after some more iterations, i got many failures

    3. I noticed that in the ADS54Jxx GUI, in the ADS54Jxx tab there is an option to set the "En long transport Layer test pattern" (it is under the "JESD Test Patterns" box). When i set it i saw that the register 0x690000 changed from 0x80 to 0x90 and at this case, the CER is 0 (even at d1). . what does this setting do?

    4. I attached some picturesFor TI.docxFor TI.docx

    Yuval

  • Yuval,

    You have to enable the "Overlay Unwrap Waveform" to get the red line. See attached.

    When you enable the long transport test pattern, the ADC generates the long transport layer test pattern mode, as per section 5.1.6.3 of the JESD204B specification. This is a fixed repeating test pattern. As long as your sample size is the same as this pattern or a whole integer divide of this, the CER test should pass with no errors. This appears what you are getting.

    Regards,

    Jim

      0407.Coherent Input.pptx

  • HI,

    Have you looked at the file i sent you. I think i did everything you told me but it still does not work well.

    I still get errors on thresholds more than 900.

    Many times i see that at the beginning of the test, everything looks fine but at a sudden i start get errors on all the thresholds.

    Yuval

  • Yuval,

    Are you getting the proper red line waveform after enabling the overlay unwrap waveform? Please send a screen shot of this.

    Regards,

    Jim

  • Yuval,

    There are some issues with your waveform indicated by the spikes in the unwrapped waveform. It appears you may be providing to much amplitude. Try lowering your amplitude to match the waveform I sent you. This had a max value of ~ 50,196 codes and a min value of ~15,436 codes.

    Regards,

    Jim 

  • Hi,

    Still does not work.

    See attachment

    YuvalFor TI_1.docx

  • Yuval,

    Try using the latest version of HSDC Pro we have. This can be downloaded from the link below. This is what I am using with my setup. 

    Regards,

    Jim

     txn.box.com/.../ahct136n22fad92ji71qabmucnbh0zqa 

  • HI,

    I am trying to enter the link but i get that "The requested page does not exist"

    Yuval

  • Still errors.

    See attachmentFor TI_2.docx

  • I am still seeing spikes on your unwrapped waveform. I think the issue is with your signal generator. Can you try another one?

  • HI,

     

    I tried a different signal generator. I used SMC100A signal generator of Rohde & Schwarts.

    I ran it for almost 3 hours and t he results are much better (see attached)

     

    Yuval

  • HI,

    Do you have the same test for 8 lanes and not 4 ?

    I would like to test it also.

    Thanks,

    Yuval

  • Hi ,

    I have one more question.

    I tried to repeat the test but with a 1m cable between the boards.

    I saw that in most of the cases, i can capture the data but sometimes i get a "Time Out Error". What does it means ?

    Also, when i tried to run the CERFor TI_3.docx test, i see that after 1 cycle it stops. Can you explain why?

    I added some photos.

    Thanks,

    Yuval

  • Yuval,

    Is this a FMC-to-FMC 1m cable you are using? The time out error usually means the clocks are not getting through. For 8 lane mode, this would require a firmware modification but we do not have the manpower right now to create this new firmware. I am not sure why the test is stopping after 1 cycle. I thought you had this running over night before. Also make sure you are providing at least 4 Amps of 5V to both boards.

    Regards,

    Jim

  • HI,

    1.  "Is this a FMC-to-FMC 1m cable you are using"? YES

    2. ."I am not sure why the test is stopping after 1 cycle. I thought you had this running over night before" - it ran overnight when the boards were connected board to board (without a cable). When i added the cable, the CER stopped after 1 cycle.

    Yuval

  • Yuval,

    May be an issue with signal integrity using this cable. You could try increasing the JESD swing using register 0x1B in page 6A00. Does the normal capture mode work? Does this work if using continuous capture? Is SYNC dropping out?

    Regards,

    Jim

     

  • HI,

    1. Increasing the JESD swing did not help, The cycle count still stops at 1

    2. When i run the continuous capture, it stops after a short time with a "Time out error" message. I do not know exactly how many cycles ran until it stopped.

    Yuval

  • Yuval,

    I am afraid the issue is with the cable. Try running the eyescan tool to see if you can improve the eye opening for each lane. This can be found under the Instrument Options tab. Select SERDES Test Options. When the EyeQ scan tool opens, it defaults to lane 0. Click on "Start" and after 100 iterations, the eye diagram will show up for that lane. Do this for all lanes with the ADC running a normal output. There are options then to adjust the equalization gain for both AC and DC that may or may not improve the eye if needed. After changing a setting, click on the "Apply" button before clicking on "START" again.

    I suggest running this tool first without your cable.  

    Regards,

    Jim

  • HI,

    I already did the eye test but the results for the 10Gbps are awful. BTW, for the 5Gbps rate, the eye looks fine so it is not that the cable is bad but probably the cable characteristics together with the PCB layout ruining the signal. 

    I remember that i also tried to change the equalization gain but it did not help, the eyes look weird and the continues grab fails after a while.

    1. how should i know how to change the  EQ DC/AC gain ?

    2. In addition, when I change the EQ DC/AC gain, close the window and grab data. When i return to the Serdes Test option window, I see that the values of the EQ DC/AC gains returned to '1'. Why?

    3. Are the EQ DC/AC gain parameters part of the ADC registers? means, when I change the values of the EQ DC/AC gain, do I change the ADC registers? if yes, which registers are changed ?

    Thanks,

    Yuval

  • Yuval,

    1. make a change do a capture, see if the eye improves.

    2. Not sure why this is.

    3. These are FPGA gain settings not the ADC.

    Regards,

    Jim

  • 1. Following your answers to (1) + (2) from my previous message. That is what I did. I changed the EQ DC/AC gain and did a capture to see if it helped. The problem was that when I returned back to the Serdes Test option window, I saw that all the parameters are again '1' so I do not know if my changes to the EQ DC/AC gain have been implemented. How can I verify they did?

    2. This is a different kind of question. When I grab data with no signal at the input, I see two spikes on the frequency domain at 245.76M (which is 983.04M / 4) and very close to 983.04M. Can you explain why these spikes exist?

    Thanks,

    Yuval

  • Yuval,

    For #1, our software team is looking into this.

    For #2, the device has a DC corrector engine to correct the 4 ADC core offsets. This removes the Fs/4 and Fs/2 spur in the FFT spectrum. But this engine needs an input tone to work properly. With no input, the correction does not work and the Fs/4 spur shows up. It also does not work with DC signals. In this case, the users would bypass or freeze the offset correction. More info can be found in the data sheet.

    Regards,

    Jim

  • Hi,

    i have few more questions:

    1. I consider to connect the ADC outputs directly to an optical transceiver and send it over a 100m fiber. Do you see any technical issues that i should think of?

    2. I saw in the data sheet and also measured by myself the BW of the ADC. I saw that it isn't smooth and have oscillations.. Can you explain the reason of the oscillations.

    Thanks,

    Yuval

  • Yuval,

    See attached regarding question #1.

    For question #2, the data sheet looks this way because it is using de-embedding, which attempts to remove the parasitics from the measurement – like balun, pcb traces, connectors etc.

    Regards,

    Jim

    JESD over Fiber.pdf

  • HI,

    1. I still did not get from you an answer regarding my question (1) from 16.7.20

    I am trying to change the EQ DC/AC gains to see if it helps me to transmit a 10Gbps over 1-5m cables (currently the test fails)

    I changed the EQ DC gain in the "Serdes test option" but I am not sure they change anything. I also did not find these registers in the data sheet so I did not know what to read in order to verify that the changing of the EQ DC/AC gains occurred (I read registers 0x44 and 0x52 on page 6800 but I am not sure these are the correct registers, anyway they did not change, both remain 0).

    2. what is the purpose of "DC OFFSET CORR BW" register. Can I use it to improve things ? do you recommend to change it or not (leave default)?

    Thanks,

    Yuval 

  • Yuval,

    Please download the last version of the data sheet (April 2019). This shows registers 0x44 and 0x52 in page 0x6800. After writing to these registers, you must do a digital reset (page 0x6800 address 0x00, bit 0) for these values to take effect. This is for digital gain. This will not help with signal integrity.

    For JESD swing adjustments, use register 0x1B in page 0x6A00. This is the register you should be adjusting for signal integrity.

    For #2, see attached. This will only help with notching out the spur at Fs/4.

    Regards,

    Jim

    ADS54J60_Fs_by_4_Correction_Cust_7_21_20.doc

  • Hi,

    I changed the "JESD Swing" but it did not help but i thought that the EQ DC/AC gains in the "Serdes test option" may help too. Maybe i do not understand the function of it.

    When I change the EQ DC/AC gains, how does it impact the signal ?

    Can I use it to improve the JESD SI so the FPGA will not crash?

    Yuval