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ADS54J60EVM: ADS54J60EVM

Prodigy 160 points

Replies: 33

Views: 178

Part Number: ADS54J60EVM

HI,

I have the evaluation board of of the ADS54J60 (these are actually 2 boards: one is with the A2D, the other is with the FPGA).

1. I want to test the BER of the ADC using the "ADS54Jxx GUI v1.6" and the "High Speed data converters Pro" programs.

I did not find how to do it. I saw an option to enable the test pattern but did not see any option to verify if all the data arrived correctly to the FPGA or not. I did not find a way to count BER errors.  How it can be done?

2. I saw that in the "High Speed data converters Pro" program, in the "instrument option" tab, under "SERDES test options" there is a way took at the eye and at the side there is a color BER bar. According the color it is hard to say if i had BER errors or not. Is there a way to read the BER counter and not to rely on the bar colors?

Thanks,

Yuval

  • Guru 63490 points

    Yuval,

    BER was implemented only to a few specific devices, as it requires special data packing to be handled in the firmware. I do not believe we had a firmware build for this part. We are looking into this.

    What LMFS setting are you using and at what ADC sample rate?

    Regards,

    Jim

  • In reply to jim s:

    Hi,

    I am following the instructions in SLAU629A so the sample rate is 983.04M.

    I try 3 types of LMFS: 8224, 4244 and 4211

    Yuval

  • Guru 63490 points

    In reply to Yuval Minster:

    Yuval,

    There is a chance we may have something that works (4211 mode) for you as is. Please follow the instructions below that were provided by our software development team.

     

    1.       Make sure the “Devices and File Info.ini” file is edited under the TSW14J56RevD folder. This file is located at the following location:

    “C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J56revD Details\Device and File Info.ini”. In this file you need to  remove the comment “CER Validate Error Count” under the ADC section.

     

    2.  Copy the provided ADS54J60_LMF_4211_CER.ini to the following location:

    “C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J56revD\ADC files”.

     

     

    3.      The  Input Sine Tone, ADC Sampling clock and FPGA Reference clock must all be synchronized.

     

    4.       The Input Sine Frequency (Fin), ADC sampling Frequency (Fs) and Number of samples per clock(N) (entered in HSDC pro GUI) must be in an relation, such that each cycle taken in CER test iteration must contain discrete number of samples which will be repetitive in successive cycle (refer point 5).

    We have a “coherent frequency calculator” utility to compute the input sine wave frequency (Fin) in relation to Fs and N. The utility can be found in the Coherent Frequency Calculator folder attached.

     

    5.       All CER testing related information are added in the attached file called “HSDC Pro FAQ & Troubleshooting Guide.docx”.

     

    Refer the Section “How to Measure Code Error Rate (CER) in TSW14J57(applicable to J56 also)

    The steps to use the calculator utility will be explained in under “Using Coherent Frequency Calculatorsubdivision. The relation between Fs, Fin and N is explained in “overview” subdivision.

     

    6.       The No. of samples per cycle (N) in HSDC pro GUI has a range minimum of 2^ADC_resolution maximum of 131072 samples and it must be multiple of 4 for this mode.

    Regards,

    Jim

    CER.zip

  • In reply to jim s:

    HI,

    1. I could not open the file "Device and File Info.ini". When i tried to open with notepad++, i got unreadable signs. What am i doing wrong?

    2. My eval board has the J60 device. I hoe that your instructions work for J60 also.

    Thanks,

    Yuval

  • Guru 63490 points

    In reply to Yuval Minster:

    Device and File Info.iniYuval,

    See if you can replace your copy of the Device and File Info.ini with the one attached. This one has the changes made. I was able to open this file using notepad. Not sure why you are having issues with this. I have not had a chance to test this but it should work for the ADS54J60 device.

    Regards,

    Jim

  • In reply to jim s:

    Thanks, I got the file and even could open it.

    Regarding the parameter (CER Validate Error Count) that you asked me to remove its comment, i did not see it under the ADC section as you said but under the DAC section. Is it OK?

    [ADC]
    Menu Disable = "Number of Channels;OnBoard Diagnostics;CER Testing;IO Delay;JESD204B Error Injection"
    Disable Controls = Pattern Verifier;TSW14J56 TRANSMITTER;CONFIG;IO Delay;Calibrate-Individual Lane Info;Debug Features"

    [DAC]
    Menu Disable = "Cursor Lock;2 Channel Display;Save Raw ADC Codes as Binary File;Import Binary File;Import Data File;Notch frequency bins;Capture Option;Number of Channels;dBFs;Analysis Window Markers;Other Frequency Options;User Profiles;NSD Marker;OnBoard Diagnostics;CER Testing;Phase Plot;Phase in Degree;IO Delay;JESD204B Error Injection"
    Disable Controls = "CER Validate Error Count;Pattern Verifier;Delay in µs;Number of Triggers;Arm On Next Capture;Info"

  • Guru 63490 points

    In reply to Yuval Minster:

    I did the edit for you already. The parameter can stay in the DAC section as you are not using a DAC.

  • In reply to jim s:

    HI,

    I tried today to run the CER test but without success.

    here is what i did (please tell me what did i make wrong):

    ADS54J60 GUI Configuration

    1. Configured the clock to 983.04MHz

    2. Programmed the "ADS54J60_LMF_4211.cfg " file

     

    HSDC Pro GUI Configuration

    3. selected in the ADC drop-down menu the file ADS54J60_LMF_4211_CER (as a sequence it downloaded the FW automatically)

    4. Entered 983.04M in the ADC Output Data Rate field

    5. Reset the board and did one capture (works fine)

     

    Run CER TEST

    6. I connected a 120KHz sine wave to input A of the ADC (I tried both 1dBm and 10dBm).

    7. I inserted 8192 into the “No. of sample per cycle” field

    8. In the “Threshold” field I inserted the number 100 (i did it only to threshold #1). Is it correct? how do you define this number? BTW, why there are 5 thresholds?

    9. Pressed the start button.

     

    I got many failures. What did i do wrong?

    BTW, Is there a way to reset the counters without closing the program ?

     

    Yuval

  • Guru 63490 points

    In reply to Yuval Minster:

    Yuval,

    See attached for more help with this testing.

    Regards,

    Jim

    CER Testing Help.docx

  • In reply to jim s:

    HI Jim,

    Thanks for your support.

    Unfortunately it still does not work.

    This is what I did:

    1. I configured the boards with the ADS54J60_LMF_4211_CER and verified that i can grab a sine wave.

    2. I entered the CER testing window and in the "No of sample per cycle" I entered the number 81920.

    3. I configured the signal generator to 132K, 10dBm

    4. I entered at threshold 1 the value 100 and press the start test.

    5. The error counter constantly increased.

    6. The weird thing is that i tried to increment the value of the threshold but it did not help. I even entered the value 70000 which must give you zero errors but the error counter still increments.

    Please tell me what am i doing wrong.

    Thanks,

    Yuval