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ADS1224: What is the frequency Response Near 50Hz and 60Hz with fCLK = 870kHz?

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Replies: 5

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Part Number: ADS1224

Hi team

My customer wants to know how well the frequency response near 50Hz and 60Hz if using the 870kHz fCLK? Datasheet only display the response curve with fCLK = 910kHz in figure 22.


Due to the accuracy issue, my customer can't achieve the accurate 910kHz clock, and the achievable clock is about 870kHz, this is why the customer asking this question.

Thank you.

  • Hi Sidong,

    The filter notches scale with frequency.  870kHz is about 95.6% of 910kHz and the filter notch would lower by the same percentage.  If the filter notch is at 55Hz, then 95.6% of the notch value is 52.6 Hz.  So for figure 22 of the ADS1224 datasheet you would slide the response curves to the left about 2.5 Hz.

    Best regards,

    Bob B

  • In reply to Bob Benjamin:

    Hi Bob

    Thanks for your reply.

    I have other questions:

    1. For the standby mode timing, the time slot t11 (Data ready after exiting Standby mode) is about 28ms in figure28. It seems that this value is given for 2MHz clock, why am I not sure is that I don't see a symbol indexed by (2) in figure 28. My question is that if using 870kHz clock what is the time t11 in this condition? if the description under this table is right for t11, the answer should be about 64ms according to the frequency ratio, is my understanding right?

    2. I am not sure whether delta-sigma ADC has the sample and conversion concepts that occur in the SAR-ADC. Is the analog signal to be converted a signal of at a certain moment or during a period of time for delta-sigma ADC? If there is a change in the analog signal during sampling (if the concept "sample" owns in the delta-sigma ADC conversion process), does that affect the output digital result?

    Thank you.

  • In reply to Shawn_Wang:

    Hi Sidong,

    See my responses below.

    Best regards,

    Bob B

    Sidong Wang1

    Hi Bob

    Thanks for your reply.

    I have other questions:

    1. For the standby mode timing, the time slot t11 (Data ready after exiting Standby mode) is about 28ms in figure28. It seems that this value is given for 2MHz clock, why am I not sure is that I don't see a symbol indexed by (2) in figure 28. [Bob] There is a typo in the datasheet and the note under the table should have been labeled (1). My question is that if using 870kHz clock what is the time t11 in this condition? if the description under this table is right for t11, the answer should be about 64ms according to the frequency ratio, is my understanding right? [Bob]  (2MHz / 870kHz) * 28.1ms and solving for x = 28.1ms * (2 / 0.87) = 64.6ms.  So it appears your understanding is correct.

    2. I am not sure whether delta-sigma ADC has the sample and conversion concepts that occur in the SAR-ADC. Is the analog signal to be converted a signal of at a certain moment or during a period of time for delta-sigma ADC? If there is a change in the analog signal during sampling (if the concept "sample" owns in the delta-sigma ADC conversion process), does that affect the output digital result? [Bob] The Delta-Sigma ADC is different from a SAR in that it is an oversampling device that converts the input to a modulator bit stream that is then followed by a low-pass digital filter.  The benefit is a higher level of precision due to lower noise.  The noise of quantization is shifted into the higher frequency domain which is then filtered out by the digital filter.  If there is a small change due to noise, then depending on the frequency and duration of the noise the output code may reflect the average of the signal plus the noise.  If there is an abrupt change (like a significant DC input level change) then due to the nature of the Sinc3 digital filter it will take 3 conversion cycles for the digital filter to fully settle.  See Figure 23 and the discussion at the top of page 13 of the ADS1224 datasheet.

    Thank you.

  • In reply to Bob Benjamin:

    Hi Bob

    I really appreciate your kindness and there are other questions that need your help:

    1. Under what condition or application would you recommend enabling the buffer inside ADS1224?

    I do understand that the enabled buffer will increase the input impedance of ADS1224 greatly, which would guarantee a more accurate sampling and make the sampling closer to the actual input signal connected to the input pins. However, compared to the condition without buffer, I also find that an enabled buffer will have a slightly poor effect on the system performance like input voltage range, INL, gain error, and gain error drift, which shown on page 3.

    In brief, the buffer is more like a double-edged sword and I feel confused about the suitable usage. This is why I ask this question.

    2. How well is the power consumption for ADS1224 under the 870kHz clock?

    On page 4 of the datasheet, the power consumption is shown with the 2MHz clock, could you please tell me that what is the AVDD and DVDD power consumption with 870kHz clock rather than 2MHz? I am not sure if the total power consumption is also proportion with the clock frequency.

    Thank you.

  • In reply to Shawn_Wang:

    Hi Stone,

    Seem my responses below.

    Best regards,

    Bob B

    Stone Wang

    Hi Bob

    I really appreciate your kindness and there are other questions that need your help:

    1. Under what condition or application would you recommend enabling the buffer inside ADS1224?

    I do understand that the enabled buffer will increase the input impedance of ADS1224 greatly, which would guarantee a more accurate sampling and make the sampling closer to the actual input signal connected to the input pins. However, compared to the condition without buffer, I also find that an enabled buffer will have a slightly poor effect on the system performance like input voltage range, INL, gain error, and gain error drift, which shown on page 3.

    In brief, the buffer is more like a double-edged sword and I feel confused about the suitable usage. This is why I ask this question. [Bob] Yes you are correct.  Don't use the buffer unless you absolutely need to.  As far as determining error, if the operation becomes marginal you need to analyze which errors will dominate.  An RSS of the errors (all in the same units of measurement) needs to be evaluated to determine the overall impact.  If you were to buffer with an external op amp buffer, you would need to also consider the impact of the noise, offset and gain error of the external buffer too.

    2. How well is the power consumption for ADS1224 under the 870kHz clock?

    On page 4 of the datasheet, the power consumption is shown with the 2MHz clock, could you please tell me that what is the AVDD and DVDD power consumption with 870kHz clock rather than 2MHz? I am not sure if the total power consumption is also proportion with the clock frequency. [Bob] The power will lower, but probably not as much as you think for the analog.  The digital power will likely lower more as a scaling as the power directly relates to the clock.  For the analog there are factors such as supply voltage and buffer that may be a big difference as compared to the clock speed.  I don't have any specific data to tell you what to expect, but there are some Figures 1 through 5 in the datasheet that can give you an idea of the trends.

    Thank you.

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