Part Number: DAC38J82
Good day to all!We use the DAC38J82 and it works fine, but sometimes the DAC PLL is out of lock.When reading the DAC registers, the difference is only in the memin_pll_lfvolt (config49), if everything works fine then it is 100, if the problem is with the DAC PLL then it is 011.Both values memin_pll_lfvolt are valid. What could be the problem that the DAC PLL is out of lock?I attached two files with DAC registers. DAC_GOOD.txt - DAC works correctly, DAC_BAD.txt - when DAC PLL is out of lock.DAC_GOOD.txtDAC_BAD.txt
I cannot understand the file format you sent. Can you format to read as follows:
0x00 0x00 where the first value is the address and the second value is the data.
Either that or explain your format.
What frequency and amplitude is your reference clock used by the PLL? Is this a clean source?
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In reply to jim s:
here is a files with format as you asked:
As reference clock we use LMK04828, if it needed I can send a registers configuration. Frequency is 140 MHz, amplitude not measured.
In reply to Evgeniy Fedosov:
Can you send a schematic showing how the LMK is connected to the DAC? What format is this clock output from the LMK?
After looking at you files it appears you are targeting the 4GHz VCO and locking it at 4480MHz, correct? One setting that is different from yours and what our GUI uses is the lock detect parameter. Have you tried increasing this by using 010 for bits 15:13 in address 0x31?
Since 4480Mhz is near the edge of both VCO ranges, you may also want to try the 5GHZ VCO to see if this is more stable.
yes we use 4 GHz VCO and locking at 4480 MHz. No we haven't tried increasing lock detect window.
Thanks for suggestion, we will try to icrease lock detect window and use 5 GHz VCO.
Here is a schematic of LMK and DAC circuits, clock output is LVPECL format:
If your schematic looks as shown, please try using LCPECL mode for the SYSREF clock output from the LMK as it appears you copied what is used on the TI EVM. With this resistor network and using LCPECL mode, the common mode voltage to the DAC will be correct for this input.
thanks for suggestion, we will try.
we tried to use 5 GHz VCO and inreased lock detect window. Log file in attachment.
What was the result of this test? You did not mention anything.
I'm sorry, I will make result later. I need some time to discribe it.
Excuse me for no answer long time.
There is no problem when we use scheme 1. PLL DAC and JESD works well, LOOP FILTER VOLTAGE is 100 (0x31 bits 2:0). See log file “7183.DAC_GOOD.txt”
But when we use external signal generator like N5173 (see scheme 2) we’ve got PLL DAC error - LOOP FILTER VOLTAGE become 011. See log “5736.DAC_BAD.txt”
When we set 5 GHz VCO loop filter voltage=000 in both situation. See log “DAC_VCO_lockwindow_change.txt”.
Changing LOCK DETECT WINDOW has no effect.
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