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DAC38J82: Problem with DAC PLL is out of lock sometimes

Part Number: DAC38J82
Other Parts Discussed in Thread: LMK04828

Good day to all!

We use the DAC38J82 and it works fine, but sometimes the DAC PLL is out of lock.
When reading the DAC registers, the difference is only in the memin_pll_lfvolt (config49), if everything works fine then it is 100, if the problem is with the DAC PLL then it is 011.
Both values memin_pll_lfvolt are valid. What could be the problem that the DAC PLL is out of lock?

I attached two files with DAC registers. DAC_GOOD.txt - DAC works correctly, DAC_BAD.txt - when DAC PLL is out of lock.

DAC_GOOD.txt
80A11800
81000300
82208200
83F00000
84FFFF00
85FF0700
86FFFF00
87230000
88049300
891F0000
8A000000
8B000000
8C030000
8D030000
8E040000
8F040000
90000000
91000000
92000000
93000000
94000000
95000000
96000000
97000000
98000000
99000000
9A000000
9B340800
9E999900
9F998000
A0800800
A21B1100
A301FF00
A4003000
A5200000
A6000000
AD000100
AEFFFF00
AF000400
B0000000
B1040400
B2072000
B3E41000
B4000000
BB980000
BC805000
BD008800
BE010800
BF000000
C1000000
C2000000
C3000000
C4000000
C6004400
C719C800
C8314300
C9000000
CA032100
CB080100
CC090100
CD010000
CE0F0F00
CF1C4100
D0000000
D100DF00
D200FF00
D3000000
D400FF00
D500FF00
D6000000
D700FF00
D800FF00
D9000000
DA00FF00
DB00FF00
DC113300
DE000000
DF012300
E0576400
E1021100
E4000000
E5000000
E64F0F00
E7FF0F00
E8FF0F00
E9FB0B00
EAFF0E00
EBF30D00
EC000600
ED00F000
EE000000
EF000000
F0000000
F1000000
F2000000
F3000000
F4000000
F5000000
F6000000
F7000000
F8000000
F9000000
FA000000
FB000000
FC000000
FD000000
FF800A00
DAC_BAD.txt
80A11800
81000300
82208200
83F00000
84FFFF00
85FF0700
86FFFF00
87260000
88049300
891F0000
8A000000
8B000000
8C030000
8D030000
8E040000
8F040000
90000000
91000000
92000000
93000000
94000000
95000000
96000000
97000000
98000000
99000000
9A000000
9B340800
9E999900
9F998000
A0800800
A21B1100
A301FF00
A4003000
A5200000
A6000000
AD000100
AEFFFF00
AF000400
B0000000
B1040300
B2072000
B3E41000
B4000000
BB980000
BC805000
BD008800
BE010800
BF000000
C1000000
C2000000
C3000000
C4000000
C6004400
C719C800
C8314300
C9000000
CA032100
CB080100
CC090100
CD010000
CE0F0F00
CF1C4100
D0000000
D100DF00
D200FF00
D3000000
D400FF00
D500FF00
D6000000
D700FF00
D800FF00
D9000000
DA00FF00
DB00FF00
DC113300
DE000000
DF012300
E0576400
E1021100
E4F70300
E5F70300
E6DF0F00
E7DD0F00
E8FF0F00
E9FF0F00
EACF0F00
EBF30E00
EC000700
ED00F000
EE000000
EF000000
F0000000
F1000000
F2000000
F3000000
F4000000
F5000000
F6000000
F7000000
F8000000
F9000000
FA000000
FB000000
FC000000
FD000000
FF800A00

  • Evgeniy,

    I cannot understand the file format you sent. Can you format to read as follows:

    0x00  0x00   where the first value is the address and the second value is the data.

    Either that or explain your format.

    What frequency and amplitude is your reference clock used by the PLL? Is this a clean source?

    Regards,

    Jim

  • Jim,

    here is a files with format as you asked:

    5736.DAC_BAD.txt
    0x00 0xA118
    0x01 0x0003
    0x02 0x2082
    0x03 0xF000
    0x04 0xFFFF
    0x05 0xFF07
    0x06 0xFFFF
    0x07 0x2600
    0x08 0x0493
    0x09 0x1F00
    0x0A 0x0000
    0x0B 0x0000
    0x0C 0x0300
    0x0D 0x0300
    0x0E 0x0400
    0x0F 0x0400
    0x10 0x0000
    0x11 0x0000
    0x12 0x0000
    0x13 0x0000
    0x14 0x0000
    0x15 0x0000
    0x16 0x0000
    0x17 0x0000
    0x18 0x0000
    0x19 0x0000
    0x1A 0x0000
    0x1B 0x3408
    0x1E 0x9999
    0x1F 0x9980
    0x20 0x8008
    0x22 0x1B11
    0x23 0x01FF
    0x24 0x0030
    0x25 0x2000
    0x26 0x0000
    0x2D 0x0001
    0x2E 0xFFFF
    0x2F 0x0004
    0x30 0x0000
    0x31 0x0403
    0x32 0x0720
    0x33 0xE410
    0x34 0x0000
    0x3B 0x9800
    0x3C 0x8050
    0x3D 0x0088
    0x3E 0x0108
    0x3F 0x0000
    0x41 0x0000
    0x42 0x0000
    0x43 0x0000
    0x44 0x0000
    0x46 0x0044
    0x47 0x19C8
    0x48 0x3143
    0x49 0x0000
    0x4A 0x0321
    0x4B 0x0801
    0x4C 0x0901
    0x4D 0x0100
    0x4E 0x0F0F
    0x4F 0x1C41
    0x50 0x0000
    0x51 0x00DF
    0x52 0x00FF
    0x53 0x0000
    0x54 0x00FF
    0x55 0x00FF
    0x56 0x0000
    0x57 0x00FF
    0x58 0x00FF
    0x59 0x0000
    0x5A 0x00FF
    0x5B 0x00FF
    0x5C 0x1133
    0x5E 0x0000
    0x5F 0x0123
    0x60 0x5764
    0x61 0x0211
    0x64 0xF703
    0x65 0xF703
    0x66 0xDF0F
    0x67 0xDD0F
    0x68 0xFF0F
    0x69 0xFF0F
    0x6A 0xCF0F
    0x6B 0xF30E
    0x6C 0x0007
    0x6D 0x00F0
    0x6E 0x0000
    0x6F 0x0000
    0x70 0x0000
    0x71 0x0000
    0x72 0x0000
    0x73 0x0000
    0x74 0x0000
    0x75 0x0000
    0x76 0x0000
    0x77 0x0000
    0x78 0x0000
    0x79 0x0000
    0x7A 0x0000
    0x7B 0x0000
    0x7C 0x0000
    0x7D 0x0000
    0x7F 0x800A

    7183.DAC_GOOD.txt
    0x00 0xA118
    0x01 0x0003
    0x02 0x2082
    0x03 0xF000
    0x04 0xFFFF
    0x05 0xFF07
    0x06 0xFFFF
    0x07 0x2300
    0x08 0x0493
    0x09 0x1F00
    0x0A 0x0000
    0x0B 0x0000
    0x0C 0x0300
    0x0D 0x0300
    0x0E 0x0400
    0x0F 0x0400
    0x10 0x0000
    0x11 0x0000
    0x12 0x0000
    0x13 0x0000
    0x14 0x0000
    0x15 0x0000
    0x16 0x0000
    0x17 0x0000
    0x18 0x0000
    0x19 0x0000
    0x1A 0x0000
    0x1B 0x3408
    0x1E 0x9999
    0x1F 0x9980
    0x20 0x8008
    0x22 0x1B11
    0x23 0x01FF
    0x24 0x0030
    0x25 0x2000
    0x26 0x0000
    0x2D 0x0001
    0x2E 0xFFFF
    0x2F 0x0004
    0x30 0x0000
    0x31 0x0404
    0x32 0x0720
    0x33 0xE410
    0x34 0x0000
    0x3B 0x9800
    0x3C 0x8050
    0x3D 0x0088
    0x3E 0x0108
    0x3F 0x0000
    0x41 0x0000
    0x42 0x0000
    0x43 0x0000
    0x44 0x0000
    0x46 0x0044
    0x47 0x19C8
    0x48 0x3143
    0x49 0x0000
    0x4A 0x0321
    0x4B 0x0801
    0x4C 0x0901
    0x4D 0x0100
    0x4E 0x0F0F
    0x4F 0x1C41
    0x50 0x0000
    0x51 0x00DF
    0x52 0x00FF
    0x53 0x0000
    0x54 0x00FF
    0x55 0x00FF
    0x56 0x0000
    0x57 0x00FF
    0x58 0x00FF
    0x59 0x0000
    0x5A 0x00FF
    0x5B 0x00FF
    0x5C 0x1133
    0x5E 0x0000
    0x5F 0x0123
    0x60 0x5764
    0x61 0x0211
    0x64 0x0000
    0x65 0x0000
    0x66 0x4F0F
    0x67 0xFF0F
    0x68 0xFF0F
    0x69 0xFB0B
    0x6A 0xFF0E
    0x6B 0xF30D
    0x6C 0x0006
    0x6D 0x00F0
    0x6E 0x0000
    0x6F 0x0000
    0x70 0x0000
    0x71 0x0000
    0x72 0x0000
    0x73 0x0000
    0x74 0x0000
    0x75 0x0000
    0x76 0x0000
    0x77 0x0000
    0x78 0x0000
    0x79 0x0000
    0x7A 0x0000
    0x7B 0x0000
    0x7C 0x0000
    0x7D 0x0000
    0x7F 0x800A
    

    As reference clock we use LMK04828, if it needed I can send a registers configuration. Frequency is 140 MHz, amplitude not measured.

  • Evgeniy,

    Can you send a schematic showing how the LMK is connected to the DAC? What format is this clock output from the LMK?

    After looking at you files it appears you are targeting the 4GHz VCO and locking it at 4480MHz, correct? One setting that is different from yours and what our GUI uses is the lock detect parameter. Have you tried increasing this by using 010 for bits 15:13 in address 0x31?

    Since 4480Mhz is near the edge of both VCO ranges, you may also want to try the 5GHZ VCO to see if this is more stable.

    Regards,

    Jim

  • Jim,

    yes we use 4 GHz VCO and locking at 4480 MHz. No we haven't tried increasing lock detect window.

    Thanks for suggestion, we will try to icrease lock detect window and use 5 GHz VCO.

    Here is a schematic of LMK and DAC circuits, clock output is LVPECL format:

  • Evgeniy,

    If your schematic looks as shown, please try using LCPECL mode for the SYSREF clock output from the LMK as it appears you copied what is used on the TI EVM. With this resistor network and using LCPECL mode, the common mode voltage to the DAC will be correct for this input. 

    Regards,

    Jim

  • Jim,

    thanks for suggestion, we will try.

  • Jim,

    we tried to use 5 GHz VCO and inreased lock detect window. Log file in attachment.

    DAC_VCO_lockwindow_change.txt
    0x00 0xA118
    0x01 0x0003
    0x02 0x2082
    0x03 0xF000
    0x04 0xFFFF
    0x05 0xFF07
    0x06 0xFFFF
    0x07 0x2800
    0x08 0x0493
    0x09 0x1F00
    0x0A 0x0000
    0x0B 0x0000
    0x0C 0x0300
    0x0D 0x0300
    0x0E 0x0400
    0x0F 0x0400
    0x10 0x0000
    0x11 0x0000
    0x12 0x0000
    0x13 0x0000
    0x14 0x0000
    0x15 0x0000
    0x16 0x0000
    0x17 0x0000
    0x18 0x0000
    0x19 0x0000
    0x1A 0x0000
    0x1B 0x3408
    0x1E 0x9999
    0x1F 0x9980
    0x20 0x8008
    0x22 0x1B11
    0x23 0x01FF
    0x24 0x0030
    0x25 0x2000
    0x26 0x0000
    0x2D 0x0001
    0x2E 0xFFFF
    0x2F 0x0004
    0x30 0x0000
    0x31 0x4400
    0x32 0x0720
    0x33 0x6410
    0x34 0x0000
    0x3B 0x9800
    0x3C 0x8050
    0x3D 0x0088
    0x3E 0x0108
    0x3F 0x0000
    0x41 0x0000
    0x42 0x0000
    0x43 0x0000
    0x44 0x0000
    0x46 0x0044
    0x47 0x19C8
    0x48 0x3143
    0x49 0x0000
    0x4A 0x0321
    0x4B 0x0801
    0x4C 0x0901
    0x4D 0x0100
    0x4E 0x0F0F
    0x4F 0x1C41
    0x50 0x0000
    0x51 0x00DF
    0x52 0x00FF
    0x53 0x0000
    0x54 0x00FF
    0x55 0x00FF
    0x56 0x0000
    0x57 0x00FF
    0x58 0x00FF
    0x59 0x0000
    0x5A 0x00FF
    0x5B 0x00FF
    0x5C 0x1133
    0x5E 0x0000
    0x5F 0x0123
    0x60 0x5764
    0x61 0x0211
    0x64 0x0003
    0x65 0x0003
    0x66 0xCF0A
    0x67 0xFF0B
    0x68 0xFF0F
    0x69 0xCB0A
    0x6A 0xB70A
    0x6B 0xFF04
    0x6C 0x0006
    0x6D 0x00F0
    0x6E 0x0000
    0x6F 0x0000
    0x70 0x0000
    0x71 0x0000
    0x72 0x0000
    0x73 0x0000
    0x74 0x0000
    0x75 0x0000
    0x76 0x0000
    0x77 0x0000
    0x78 0x0000
    0x79 0x0000
    0x7A 0x0000
    0x7B 0x0000
    0x7C 0x0000
    0x7D 0x0000
    0x7F 0x800A
    
    

  • Evgeniy,

    What was the result of this test? You did not mention anything.

    Regards,

    Jim

  • Jim,

    I'm sorry, I will make result later. I need some time to discribe it.

  • Jim,

    Excuse me for no answer long time.

    There is no problem when we use scheme 1. PLL DAC and JESD works well, LOOP FILTER VOLTAGE is 100 (0x31 bits 2:0). See log file “7183.DAC_GOOD.txt”

    But when we use external signal generator like N5173 (see scheme 2) we’ve got PLL DAC error - LOOP FILTER VOLTAGE become 011. See log “5736.DAC_BAD.txt”

    When we set 5 GHz VCO loop filter voltage=000 in both situation. See log “DAC_VCO_lockwindow_change.txt”.

    Changing LOCK DETECT WINDOW has no effect.

  • Evgeniy,

    Take a phase noise measurement at the output of C1 and C2 and see how they compare. I am guessing you have to much jitter in scheme 2 and the PLL cannot lock to this noise reference. Is the amplitude the same for both clocks?

    Regards,

    Jim

  • Jim,

    Yes, amplitude is the same.

    Screenshot output of C1

    Screenshot output of C2 (R&S RTO2064 + RTO-B6 option used as clock generator):

  • I think you have found your problem. C2 needs a cleaner source.

  • Jim,

    many thanks for your help.

  • Jim,

    where I can find phase noise calculation methodic for LMK04828+DAC38J82 clock system?

    or may be you can give me some advice?

  • Evgeniy,

    See the attached document for more information. In your setup, we noticed you had the lockdet_adj (config49) set to 0 (default). This is the most stringent setting. You may want to try increasing this. The PFD frequency seen by the PLL cannot exceed 160MHz, but the higher the value, the better the phase noise performance. You may want to increase your reference frequency and see if it helps.

    Regards,

    Jim

    3324.DAC38J84 Clock, PLL and SERDES Configuration.docx