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ADS1256: System clocks and ADC measurement synchronization

Niclas Arndt
Intellectual 425 points
Part Number: ADS1256

Hi,

This is a general ADC question concerning synchronization of system clocks and ADC measurements.

In the old product I am currently converting to a modern MCU, the step up regulator clock (333.333 kHz) is derived from the MCU and LCD display controller clock (8 MHz). The ADS1256 is clocked from a dedicated 7.68 MHz crystal that is not synchronized to the other clocks. According to the designer of the old hardware, these frequencies were carefully chosen (possibly together with the 1000 SPS data rate) for low interference. To me it sounds reasonable to believe that this could be the case, but I currently have little experience in this area. The SYNC#/PDWN# pin is tied HIGH.

With the modern 120 MHz MCU, there is now the possibility of interconnecting timers so that all of the above is synchronized, down to generation of SYNC#/PDWN# pin pulses in phase with ADS1256 XTAL1/CKLIN.

In my particular case, 7.5 MHz and 10 MHz ADS1256 clock frequencies 'work out with the rest'.

Strictly speaking, not all of the timers have to be in phase, as the master timer is either a prescaler or a 'gate controller' to the three slaves that can be started at another counter value than 0. (ADS1256 CLKIN and SYNC#/PDWN# must be in phase in order for timing requirements to be met).

In other words, I have already checked that it _can_ be done (with LCD at 60 MHz and step up regulator clock at 312.5 kHz), but is it a good idea to do it? (Synchronizing all of the above.)

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Alternatively, it is possible to interconnect two timers that generate LCD display clock and step up regulator clock in phase with each other _and_ two timers that generate ADS1256 CLKIN and SYNC#/PDWN# in phase with each other. These two pairs of interconnected timers are two independent timer pairs. The benefit would be greater flexibility and more viable frequencies compared to the first alternative.

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I understand that this is potentially a very complex question and that it may be situation-specific, but please see what you can do.

Please don't focus on the particular frequencies. The advice I am seeking is on a conceptual level. (How) does ADC measurements benefit from synchronization with other/all parts of the system?

Thank you and best regards

Niclas

  • 0
    TI__Mastermind 35141 points

    Hi Niclas,

    Having synchronized clocks is not bad per se, but if it requires a lot of additional circuitry to manage, which complicates routing and has the potential to couple CLK signals onto sensitive analog circuitry, then it is likely not worth it unless the application requires it.

    For slow-moving signals, clock frequency synchronization is usually not that big of an issue. In this specific case, as you have noted, there is a strict timing requirement for the SYNC/PWDN pulse that might be hard to achieve with misaligned clocks. Therefore, meeting timing specs and communication time requirements might be another reason to maintain clock synchronization. For example, maybe you have multiple devices on an SPI bus. Or, if you need to synchronize system events e.g. 2x ADCs sampling at the same time.

    There really isn't a "yes" or "no" answer to this question, it just depends on the needs of the application unfortunately.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Intellectual 425 points

    Hi Bryan and thanks,

    Compared to the current HW design, we're talking about adding (routing for) a 7.5 - 10.0 MHz ADS1256 clock from the MCU. This would sync the ADS1256 to the rest of the system clocks, at the cost of potential coupling into the analog part.

    Optionally, using the SYNC#/PDWN# pin for triggering a conversion would require (routing for) another periodic signal with a LOW part at the equivalent to the CLKIN frequency / 4 (and a HIGH part that's adjustable based on the desired number of used conversions / s). This is also at the cost of potential coupling.

    If we here disregard emission spectrum and such issues, is the potential gain of clock synchronization (or at least the choice of clock frequencies regardless of synchronization) that you can notch filter out certain frequencies based on sampling data rate?

    Or, put differently: do you lose the point of careful system clock frequencies selection if you don't match it to the notch filtering?

    In my case, the signals will be DC (or very close to it), so as you say it might not be that much of an issue, but I still need to understand the reasoning on this topic.

    Best regards

    Niclas

  • 0 in reply to Niclas Arndt
    TI__Mastermind 35141 points

    Hi Niclas,

    I believe you are asking if choosing specific frequencies will allow those frequencies to be rejected by the ADC's digital filter - let me know if that is not the case. The ADC's digital filter will have nulls at multiples of the output data rate. So, if you are sampling at 1kSPS, these nulls will be at 1kHz, 2kHz, 3kHz and so on. The CLKIN frequency (7.68 MHz typ) will not be rejected by the digital filter as the digital filter has unity gain at multiples of the modulator data rate (see Figure 16). The analog anti-aliasing filter you should have at the input to the ADC is responsible for rejecting these frequencies.

    The 330 kHz frequency could be rejected by the digital filter if it coupled into the system prior to the filter, but keep in mind that any variation in this frequency (since all clocks have a tolerance) could start to move up the frequency lobe and reduce the overall rejection. Also keep in mind that the data rates shown in Table 11 scale with CLKIN, so using 7.5 MHz for example will give you different data rate options and therefore different frequency nulls.

    In general, clock synchronization is more important for AC measurements where you are concerned about SNR and THD. For DC measurements, it is still important, but unless the clock source has significant jitter it should not add a significant amount of noise to the system. Here is some additional information about clocking noise and best practices: https://www.allaboutcircuits.com/industry-articles/resolving-the-signal-part-10-how-clock-signals-affect-precision-adcs/

    -Bryan

  • 0 in reply to Bryan Lizon86
    Intellectual 425 points

    Hi Bryan,

    Thanks a lot for all the help and advice,

    Best regards

    Niclas