Part Number: ADS131A04
I’ve got a question regarding the ADS131A04:
Is my following calculation correct:?
The maximum CLKIN is 25 MHz (7.3). Therefore the maximum ICLK(=SCLK) (see table 18.104.22.168) is 12.5MHz.
If crc and hamming code is deactivated. SCLK should be at least:
Therefore the maximum ADC data-rate per channel in synchronous master mode with 24bit is 85333kSPS.
I believe that's correct. With synchronous master mode, the SCLK is derived from the master clock and the fastest setting is set with fCLKIN/2.
With a lower DVDD, you could run fCLKIN as fast as 25MHz (clock period of 40ns as listed in the datasheet). After that, you could use the dynamic frame mode for communications with the CRC disabled. Each frame would be five 24-bit words for communication. If you were only using three channels instead of four, you could run the device even faster.
Note that the data rate will scale with fCLKIN. By running fCLKIN at 25MHz, this changes what you get out for fMOD and will scale the data rate.
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In reply to Joseph Wu:
Just for clarification : You wrote that DVDD should be lower to have a higher CLKIN frequency, but according to “7.3 Recommended Operating Conditions” IOVDD should be greater than 2,7V to have a maximum clock frequency of 25MHz.
What do you think?
In reply to Rui Zhang35:
You're correct, I made that mistake. That clock frequency should have been for IOVDD from 2.7V to 3.6V. Lower voltages are slower.
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