Part Number: ADS1283
I'm beginning to work on a new ADS1283 design, and I want to achieve the best performance possible. I'm wondering about the influence of two design factors on the performance of the part.
1.) The datasheet advises to connect a 1uF capacitor to the BYPAS pin in order to support the internal regulator. Has TI done any testing to support whether increasing this value would offer any performance improvement? Or perhaps combining several different carefully-chosen capacitor values (in order to yield a low impedance over a wider bandwidth) would help? It is easy to place a larger value in this position, so if it would improve performance even by a small amount, I would do that.
2.) Generally speaking, data converters benefit from high-performance clocks with low phase noise. Is that also the case with the ADS1283? I'm wondering how much effort and expense I should put into placing a high-performance, low-jitter 4.096MHz clock into my design. Like the question above, I'm trying to bias for highest performance.
If there are any other design factors that TI has observed which result in even small additional performance gains, I'd be grateful to know about them. Of course I'm already paying attention to all of the usual factors like good layout and grounding design, low-noise power supplies, proximity to aggressor noise sources, etc.
Best regards,Chris HallApplications Engineer | Precision ADCs
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In reply to Christopher Hall:
Exactly the sort of info I was hoping for - many thanks for the details and quick response Christopher!
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