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ADS1283: Design factors which affect performance

Josh Heiner
Intellectual 860 points
Part Number: ADS1283
Other Parts Discussed in Thread: REF5050

Hi,

I'm beginning to work on a new ADS1283 design, and I want to achieve the best performance possible.  I'm wondering about the influence of two design factors on the performance of the part.

1.) The datasheet advises to connect a 1uF capacitor to the BYPAS pin in order to support the internal regulator.  Has TI done any testing to support whether increasing this value would offer any performance improvement?  Or perhaps combining several different carefully-chosen capacitor values (in order to yield a low impedance over a wider bandwidth) would help?  It is easy to place a larger value in this position, so if it would improve performance even by a small amount, I would do that.

2.) Generally speaking, data converters benefit from high-performance clocks with low phase noise.  Is that also the case with the ADS1283?  I'm wondering how much effort and expense I should put into placing a high-performance, low-jitter 4.096MHz clock into my design.  Like the question above, I'm trying to bias for highest performance.

If there are any other design factors that TI has observed which result in even small additional performance gains, I'd be grateful to know about them.  Of course I'm already paying attention to all of the usual factors like good layout and grounding design, low-noise power supplies, proximity to aggressor noise sources, etc.

Thanks,

Josh

  • 0
    TI__Mastermind 44550 points

    Hi Josh,

    1. I'm not aware of any testing that looked at different values of capacitance on the BYPAS pin. Likely the internal regulator was designed for some minimum amount of load capacitance and increasing the capacitance may have some impact on start-up time. If I recall correctly this regulator primarily services as the supply for the digital circuitry which is typically fairly immune to supply noise.

      However, I do know that we've seen small SNR improvements on the analog side when connecting a 1-10 uF decoupling capacitor between AVDD and AVSS. Often times AVDD and AVSS are bypassed to ground, but a decoupling capacitor connected directly between these supply rails has been shown to be more effective and slightly improve the overall noise performance.

      Perhaps you've seen this post already [FAQ] PCB Layout Guidelines and Grounding Recommendations for High-Resolution ADCs. Also, be sure to use a low-noise buffered reference such as the REF5050 or any of the REF6x50 devices as reference noise is also an important factor (more details on this here: https://e2e.ti.com/blogs_/archives/b/precisionhub/archive/2015/12/11/the-impact-of-voltage-reference-noise-on-delta-sigma-adc-resolution).
       

    2. Yes and no...clock jitter is very important to minimize when you're sampling a high frequency input signal, as any uncertainty in when the signal is sampled gets translated into a measurement error (since the input signal is rapidly changing). For low frequency signals, the input signal does not change amplitude nearly as much within the jitter period so SNR is less sensitive to jitter.

      Also, the ADS1283 is an oversampling ADC with a digital filter that averages many conversion results before providing a filtered output. Assuming the clock jitter is random, this averaging also has the effect of reducing the overall clock jitter error observed.

      Here is another E2E post that provides some relationships between clock jitter, input frequency, OSR, and the maximum SNR you can achieve due to clock jitter error: https://e2e.ti.com/support/data-converters/f/73/t/890938?tisearch=e2e-sitesearch&keymatch=clock%20jitter

  • 0 in reply to Christopher Hall
    Intellectual 860 points

    Exactly the sort of info I was hoping for - many thanks for the details and quick response Christopher!

    Josh