ADS5560: Spikes on Zero Crossing and Noisy sampled signal

Felipe Plech

Prodigy 30 points

Part Number: ADS5560

Hello,

I'm using the ADS5560 ADC connected to a FPGA with the following settings:

Mode: LVDS

Sample Frequency: 10MHz

Sample Mode: Low Speed (<=25MHz)

When sampling a 32768 Hz, 300mVpp sine wave, occurs a spike on the transition from a positive value to a negative value (zero crossing) as the image below.

As you can see, there is spikes on the signal "data_out". The other samples seems to be correct, but noisy. The figure below shows the wave on the oscilloscope.

Best regards,

Felipe Plech

over 3 years ago

0 Felipe Plech over 3 years ago

Prodigy 30 points

I forgot to attach the oscillsocope image.

0 RJ Hopper over 3 years ago in reply to Felipe Plech

TI__Mastermind 18065 points

Felipe:

It looks like the spikes are occurring at the transitions where the output codes have the most transitions. In other words, each bit is transitioning so all of the overshoot/glitch is lining up. If this is binary representation, you can try to switch the ADC data to twos-complement. Otherwise your signals look reasonable.

--RJH

0 Felipe Plech over 3 years ago in reply to RJ Hopper

Prodigy 30 points

Hello Hopper,

Thank you for your reply.

I'm already using it with two's complement, I forgot to mention.

0 Vijayendra Varma Siddamsetty over 3 years ago in reply to Felipe Plech

TI__Genius 10505 points

Hi Felipe,

Are you using SPI register programming or parallel pins?

If you are using register programming, can you check ramp test pattern output? To set to ramp test pattern, you can program register 65 to value 0x80.

Regards,

Vijay

0 Rob Reeder over 3 years ago in reply to Vijayendra Varma Siddamsetty

TI__Mastermind 20060 points

Hi Felipe,

Are the digital outputs configured for CMOS or LVDS?

Regards,

Rob

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ADS5560: Spikes on Zero Crossing and Noisy sampled signal