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Original question:

ADS7953: Capacitance at REFP and REFM pins

ADS7953: Can the capacitance on Vref PIN be smaller?

feng luo
Prodigy 140 points
Part Number: ADS7953

Hi,

When we're designing a new project with ADS7953, we find it difficult to put a 10uF capacitor close to the ADC, and our another project use one external reference which can only accept 10uF maximum capacitor.

So I want to know whether the value of this capacitor can be smaller or not. In my opinoin, the external reference provide current for the internal ADC core, what if we only proide 2.2uF capacitor close to the VREF pin. Will this afffect the accuracy of the ADC, and how to quantify the effect?

Thanks.

  • 0
    TI__Mastermind 24940 points

    Hello,

    Decreasing the reference cap can have an affect on the voltage reference. The reference pin drives a switching CDAC which will experience quick transients.

    I am looking more into decreasing the cap.

    Note that the sampling rate will also affect this, the faster the sampling rate the faster the transients will occur, meaning the faster they need to recover.

    Regards

    Cynthia

  • 0 in reply to Cynthia
    Prodigy 140 points

    Hi Cynthia

    Thanks for your replying. I know what you mean, but I cannot find the C_DAC value in the datasheet. Maybe the most significant impact is that as the capacitance on Vref pin decreaseing, the voltage drop on the pin maybe larger. 

    Usually the internal caps are several pF, if we use maximum sample rate, it means the external caps on Vref pin 2.2uF should charger the internal caps within 1us， then we should take into account the resistance on charging loop, assuming the internal cap's voltage changes from 0V to 3.3V, if VREF pin's cap can charge internal caps from 0V to 3.3V within 1us, maybe it's ok for us to use 2.2uF capacitor. Am I right?

    So please help to provide the internal caps and the parastic resistance on charging loop, so that we can calculate the voltage drop in detail.

    Thanks a lot.

    Regards.

    Luo

  • 0 in reply to feng luo
    TI__Mastermind 24940 points

    Luo,

    The CDAC is the same as the input sampling capacitor of the device, in this case it would be 15pF. The CDAC is comprised of an array of capacitors that add up to that value, thus it is having to charge each capacitor at the rate of the clock being used. With each clock pulse the array switches to a new capacitor in the array. 

    The parasitic resistance is a bit more difficult to estimate, but to be on the safe side, I would suggest using the same resistor values given in the sample and hold equivalent circuit given in the datasheet. 

    You are correct that with a smaller capacitor value, the reference voltage can dip. The voltage dip can also would vary based on the sampling rate of the device. 

    We cannot provide a different recommendation of capacitor value to use other than 10uF though, this device was characterized with a 10uF cap, thus any deviation from that we cannot state how the device will perform or meet datasheet performance. 

    Regards

    Cynthia