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ADC3222: How to Connect CLK pin and Data pin to FPGA

user6083619
Prodigy 180 points
Part Number: ADC3222

Hi, Ti.

I'm designing schematic abou ADC3222.

In ADC3222 datasheet chapter 9.3.2, you describe how to connect LVDS line about CLKP/CLKM ( Add 0.1uF and 100ohm).

Can the same circuit be applied to other circuits?

Show attached file.

I designed same circuits for DCLKP/DCLKM and FCLKP/FCLKM.

CLK SPEED is 20MHz for CLKP/CLKM, 120MHz for DCLKP/DCLKM and 20MHz for FCLKP/FCLKM.

I'll set Interface option "12x".

Additionaly how about data line ( DA0P/DA0M and more )?

Ofcourse I adjust R or C parameter in each circuit considering frequency.

AD3222_FPGA.pdf

  • 0
    TI__Guru* 91947 points

    User,

    DCLK and FCLK are LVDS signals. The circuit for these should match what you are using for the output data bus DA and DB. In must cases, the 100 Ohm termination is available inside the FPGA. If this is so for your case, you could remove the resistors.

    You may lose some performance do the clock jitter from the FPGA. Most applications use a low jitter clock solution device, not the FPGA to clock the ADC. See section 9.3.2.1 regarding jitter and how it effects performance.

    Regards,

    Jim    

  • 0 in reply to jim s
    Prodigy 180 points

    Hi Jim.

    Did you advise I had better use SYSREF and Clock divider to take care of jitter?

    Can I ask more question?

    (1) Please show me how to configure SYSREFP, SYSREFM.

    If I want to set SYSREF=H , should I set SYSREFP = AVDD and SYSREFM=GND at pins?

    If I want to set SYSREF=L ,  should I set SYSREFP = SYSREFM=GND at pins?

    Why SYSREF is diffrential input?

    (2)Please show me more detail about 9.3.2.1 contents.

    Does the feature of SYSREF work when I set "CLK DIV" register to 00 or 01?

    If SYSREF feature doesn't work when "CLK DIV" register is set 00 or 01, 

    should I set "CLK DIV" register  to 02 and DCLK frequency to 40MHz ( x2 of desired freqeuncy)?

  • 0 in reply to user6083619
    TI__Guru* 91947 points

    User,

    SYSREF has nothing to do with jitter. This is only used to synchronize multiple devices. The input clock divider allows more flexibility for system clock architecture design. This will not help with jitter.

    SYSREF only works if CLK DIV is set to 0xC0 (div 4) or 0x80 (div 2). If you do not plan on using sysref, connect SYSREFP to AVDD and SYSREFM to GND.

    SSYREF is differential to avoid less chances of triggering on a glitch.

    Regarding section 9.3.2.1 see attached for more info.

    Regards,

    Jim

    7317.Clocking High Speed Data Converters - 3_17_2013.pptx