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DAC7551-Q1: Not seeing expected Vout

Part Number: DAC7551-Q1
Other Parts Discussed in Thread: REF3125, DAC7551

Hi,

I am working with the DAC7551-Q1. Attached is the datasheet: https://www.ti.com/lit/ds/symlink/dac7551-q1.pdf?ts=1592428323142&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDAC7551-Q1

The end goal is to have the DAC output a 65KHz sine wave. The only signal being seen on the DACs output (Vout) is a ~.5V DC signal.

The DAC is communicating with a Teensy 4.1 development board using the SPI interface; The DACs input clock is running at 4MHz. The DACs Vdd and the IOVdd pin are tied together and are receiving 3.3V from the Teensy 4.1 development board. The Vfb pin is tied to the Vout pin. Currently, the VrefH pin is tied to 3.3V on the Teensy 4.1. I understand that I will eventually need to provide a buffered reference (REF3125), but I am hoping using the Teensy 4.1 in the mean time is not causing any issues. Currently there are no bypass capacitors in place, but I would assume that I would still see a sine wave on the output even if it is a bit messy.

According to page 13, section 7.3.3.3 of the datasheet: "On power up, all registers are cleared and the DAC channel is updated with zero-scale voltage. The DAC output remains in this state until valid data are written." Since this is the case, why am I seeing a ~.5V signal on the output of the DAC on power up? Also, according to section 7.3.3.5 the output is set to zero-scale voltage immediately after the !CLR pin is brought low I should see zero-scale voltage, which I don't believe I am, unless I am not understanding zero-scale voltage (seeing ~.5V).

On page 14, section 7.5.1.1 of the datasheet it says that the !SYNC pin acts as a frame synchronization signal and chip enable. Currently, the !SYNC HIGH time is set to 10ms and is only asserted once before the first word. Do I need to be continuously asserting the !SYNC pin after each word or just once before the first input word?

Any help, comments, or example code will be greatly appreciated.

Thanks,

-Alex

  • Hi Alexander, 

    You should also verify that your ground connections are well established.  A simple schematic would also help.

    I generally recommend that you keep SYNC high when the bus is idle.  You assert it low before the word begins, then bring it high after the word is complete.

    Let's start with a complete schematic of your setup to see if you have a wiring issue first.

    Thanks,

    Paul

  • Thanks for the quick response Paul.

    To clarify, I need to assert SYNC low before each word, not just the fist word. Then keep SYNC high when during idle states. 

    Attached is a picture of my schematic. DAC_Schematic.pdf

    Thanks,

    -Alex

  • Hi Alex,

    Thanks for the schematic.  I only see one problem.  You have /CLR pulled low, which means the device is in the clear mode all the time. This pin is active low, so you should have a pull-up resistor on the pin and switch to connect it to ground.

    Try connecting CLR to 3.3V to debug this.

    Also, you might need to verify the SDO and SDIN pins are correct with a scope.  I have seen some MCUs list SDIN and SDO as serial-data-in and serial-data-out, in which case you have wired it incorrectly.  But I have also seen MCUs list them as slave-data-in and slave-data-out, which would mean you did not connect them correctly.  You might want to verify it.

    Thanks,

    Paul

  • Thanks for the help Paul. I soldered in a new DAC7551 chip and this fixed the problem. I am now seeing the expected sine wave on the output. I guess I did a bad soldering job on the first chip. I also pulled the /CLR pin high as per your above comment. 

    Thanks,

    -Alex