ADS112U04: Chaining WREG commands to programmatically read multiple channels one at a time. Timing and SYNC limitations?

I'm writing a driver to cyclically read multiple channels from an ADS112U04, and I have a question on the communication timing limits for writing sequential WREG/ START commands.

In my application, I'm using an external analog mux controlled by the ADS112U04's GPIO lines to expand the number of analog channels I can read, and sequentially reading ADC channels in single-conversion, automatic data read mode. Consequently, before starting each conversion, I must write to both the internal mux register and the GPIO register for the external mux.

My intended algorithm is as follows: 

1. Configure ADC for single conversion, automatic data read (so a single conversion result is returned each time I send START).
2. Perform the following for each channel in my list:
   1. Send WREG command to set GPIO pins for external mux
   2. Send WREG command to write internal mux register,
   3. Send START command
   4. Wait for data conversion result to be returned. When it arrives, repeat from step 2 for the next analog channel.

3. At the end of the channel list, repeat from step 2 from the top of the channel list,.

The questions are these:

• Can I send multiple WREG commands in a continuous stream without a SYNC word between them (only one SYNC at the start of the sequence), or must each command be preceded by its own SYNC word?
• Is there a minimum necessary delay between WREG commands to avoid command overruns in the ADC? (Note that I'm carefully NOT violating the half-duplex comm limitation, as only the final command returns data)
• Is there a minimum necessary delay between the last WREG command in the sequence and the START command that triggers a conversion?

Thanks,

Steve Hersey