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ADC12DJ3200EVM: ADC Samples Wrong

Tarun Kumar4
Prodigy 50 points
Part Number: ADC12DJ3200EVM
Other Parts Discussed in Thread: ADC12DJ3200,

Hi,

I am using TI ADC ADC12DJ3200 with Arria 10 FPGA and using example design and JMODE 0, I am trying to capture the ADC Samples. However, I am getting wrong data with very high noise value. 

I tried to debug it with Test Patterns and found it working fine with Ramp as well as Transport Layer Short Test Pattern. That say, That configuration is fine. I am using GUI by TI for doing LMK, LMX and ADC Configuration.

Let me know if any solution is available for this.

Regards,

Tarun

  • 0
    TI__Guru* 91947 points

    Tarun,

    Did you use the example firmware found on the ADC12DJ3200EVM product folder on the TI website? Can you send screen shots of the output data and the GUI settings?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 50 points

    Yes we have used the example firmware found on ADC12DJ3200EVM product folder by Migrating the design for Arria 10 EVM. As i mentioned earlier, we are getting correct test patterns. We made some progress on ADC Capture as we were able to get the signal output however in some captures, the noise level is too high. I am attaching two captures screenshot, one with signal capture and other without any input signal, to observe the noise floor

  • 0 in reply to Tarun Kumar4
    Prodigy 50 points

    Also, in the GUI Settings we are just setting Internal Clock generation and Fs as 3000 MHz along with JMODE0. We are not touching any other settings as suggested by Local FAE

  • 0 in reply to Tarun Kumar4
    TI__Guru* 91947 points

    Tarun,

    In the HSDC Pro GUI, in the ADC Output Data Rate entry, I noticed you have 6k. For mode 0, this needs to be double the Fclk rate used in the ADC GUI. For your case, this should be 6G. Give this a try.

    Regards,

    Jim 

  • 0 in reply to jim s
    Prodigy 50 points

    Jim,

    The setting of 6k was done wrong but it will just effect the FFT Bin Points and Peak Frequency. It will not create the noise issue.

    However, we were able to decipher the real issue and found out that the data formatting was incorrect. We were expecting 2s complement form but we were getting Offset binary from the ADC. On changing this setting, we were able to get proper signals and good performance as per datasheet.

    Thank you for the support.

    Regards,

    Tarun