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DAC38RF80EVM: Issue with TSW14J56revD Board when using on-board oscillator, LMK and on-chip PLL mode

Daimeng Zhang
Prodigy 60 points
Part Number: DAC38RF80EVM

Hi, I am evaluating the DAC38RF80EVM and found some issues while it is connected to the TSW14J56 revD Board.

My current configuration is: using the on-board 122.88MHz oscillator as the reference into the LMK, then LMK output serving as DACCLK and FPGA CLK. To get this working, I DNI C333 and C334 and install C2 and C3 based on the schematic. With this modification, I can see the LMK clk output into the DAC, and have the DAC PLL locked when FPGA board is turned off. The GUI configuration is shown below:

Without the FPGA board, I can control the registers of the DAC and LMK through GUI just fine, and successfully get the correct DAC output using the constant data mode.

However, once I turned on the TSW14J56revD FPGA board, the DAC eval board’s registers cannot be modified through GUI. For example, I set the LMK DCLK Divider to 9, it reads back as 31. I cannot change the N Divider of LMK and CP tri-state is always on. VCO selection is not available. Ocs-in selection is not available. And I cannot set the DAC registers in the clocking tab. As a result, the DAC PLL is shown as unlocked. 

I then tried to create patterns from the FPGA board and send to DAC board:

I got this warning: JESD REF CLK needs to be 237.0665MHz.

Then I got this error message: WRITE_REGISTER_FAILED

So I have the following questions:

1) Is this the correct configuration for using on-board 122.88MHz osc as LMK ref and LMK output as DACCLK and FPGA CLK.

2) Does the freq configuration make sense for LMK and DAC to get the correct DACCLK, FPGA CLK, JESD reference clk? Will I always get the 1st warning message about the JESD reference clk?

3) Why the FPGA board keeps resetting the registers? I tried two revD board and observed the same thing.

Thanks for your support.

  • 0
    TI__Genius 11940 points

    Hi Daimeng,

    I am looking into this and will let you know my findings.

    Regards,

    David 

  • 0
    TI__Genius 11940 points

    Hi Daimeng,

    1) Those are the correct settings to have the board use the on-board 122.88MHz oscillator, make sure a jumper is on JP3 and make sure that under the DAC38RF8x clock tab the SERDES REF CLK select is on the PLL Clock. I was able to program a DAC38RF80EVM with the same setting and could get an output with the NCO and the TSW14J56.

    2) The frequency configuration is correct. HSDC Pro will always give that first message about the JESD reference clk.

    3) The most likely reason that the registers are resetting and not allowing you to modify them is because of the power supply for the boards. If you are using the same power supply for the boards there may not be enough current for both boards. It is recommended that the TSW14J56 and DAC38RF80EVM have their own power supplies rated for about 3-4 amps. 

    Regards,

    David

  • 0 in reply to David Chaparro
    Prodigy 60 points

    Hi David,

    Thanks for looking into this. I was able to control the registers now after I removed R288 to R295. And I can send the pattern without an error message through the High Speed Data Converter Pro. However, I still cannot get an DAC output with the freq settings.

    The warnings and errors in the DAC tab:

    You mentioned that "make sure that under the DAC38RF8x clock tab the SERDES REF CLK select is on the PLL Clock." I had to change this to DACCLK in order to have the SERDES PLLs locked. Changing it to PLL CLOCK makes the PLL unlocked:

    Can you send a configuration file that works on your side with the same mode and freq configuration?

    Thanks!

    Best,

    Daimeng

  • 0 in reply to David Chaparro
    Prodigy 60 points

    Hi David,

    Thanks for looking into this. I was able to control the registers now after I removed R288 to R295. And I can send the pattern without an error message through the High Speed Data Converter Pro. However, I still cannot get an DAC output with the freq settings.

    The warnings and errors in the DAC tab:

    You mentioned that "make sure that under the DAC38RF8x clock tab the SERDES REF CLK select is on the PLL Clock." I had to change this to DACCLK in order to have the SERDES PLLs locked. Changing it to PLL CLOCK makes the PLL unlocked:

    Can you send a configuration file that works on your side with the same mode and freq configuration?

    Thanks!

    Best,

    Daimeng

  • 0 in reply to Daimeng Zhang
    TI__Genius 11940 points

    Hi Daimeng,

    There might be some setting in your GUI that is different from mine because the SERDES Ref Clock Select has to be on PLL Clock and the SERDES PLL0 and PLL1 will be locked. It might be easier for you to use my configuration file rather than search for the different settings we have.

    Here is the configuration file for my setup: LMK_DAC_VCXO_PLL.zip

    In the GUI go ahead and reset the DAC. Load the configuration file and make sure that the PLL2 Lock LED, D4, and the LMK Lock LED, D3. are on. You will need to run the PLL AUTO TUNE and Reset DAC JESD Core in order to see the correct output. 

    Also, for HSDC Pro I would suggest using a higher frequency tone, I used 50 MHz to test my configuration. There is an internal transformer that will most likely not allow a 100MHz signal to pass through and prevent you from seeing that tone on the output.

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 60 points

    Hi David,

    I can now see the DAC output with the configuration you sent, however, the SERDES PLL0 PLL1 still show as "out of Lock"... Don't know what is going on.

    The Alarm Monitoring suggests:

    sysrefphase4 state has been observed in the sysrefalign logic at least once since the last sysrefalign sync.

    sysrefphase1 state has been observed in the sysrefalign logic at least once since the last sysrefalign sync.

    align_to_r3 state has been observed in the sysrefalign logic at least once since the last sysrefalign sync.

    align_to_r1 state has been observed in the sysrefalign logic at least once since the last sysrefalign sync.

    PLL in the Rincewind0 block goes out of lock. A false alarm is generated at startup when the PLL is locking. User will have to reset this bit after start to monitor accurately.

    PLL in the Rincewind1 block goes out of lock. A false alarm is generated at startup when the PLL is locking. User will have to reset this bit after start to monitor accurately.

    "DAC A, Lane 0 multiframe alignment error"

    "DAC A, Lane 1 multiframe alignment error"

    "DAC A, Lane 2 multiframe alignment error"

    "DAC A, Lane 3 multiframe alignment error"

    "DAC B, Lane 4 multiframe alignment error"

    "DAC B, Lane 5 multiframe alignment error"

    "DAC B, Lane 6 multiframe alignment error"

    "DAC B, Lane 7 multiframe alignment error"

    - Is there any hardware change that might have caused this error and PLL unlock?

    - Which GUI are you using? I may try the same version to see if this is software issue.

    - Also, for the LMK CLK outputs tab, the SDCLKout_PD should set to high or not? A lot of times I see it's reset back to 0 after I reset DAC JESD Core and sysref trigger.

    Thanks for your support!

    Best,

    Daimeng

  • 0 in reply to Daimeng Zhang
    TI__Genius 11940 points

    Hi Daimeng,

    There are a couple of things on the hardware that could possibly cause your issues. First can you visually check and verify that C450 and C449 are removed on your board, as these add stubs to the differential clock coming from the LMK. Also, can you remove R1 as this may be allowing the 122.88 MHz LMK_DACCLKSE to feed into DAC single-ended input pin, which can cause some internal crosstalk.

    Regards,

    David

  • 0 in reply to David Chaparro
    Prodigy 60 points

    Thank you David for your support. I still cannot have the lock but am able to see accurate DAC output.

    Another related question is, now I am trying to use another set of freq configuration for interpolation of x6 and maximize the serdes rate (while lowing the dacclk), but the GUI gives a warning on invalid PLL frequency (see picture below).

    My question is:

    1) why is it invalid PLL Frequency while the serdes rate is within range <12.5GHz and DAC clk is within 7.5GHz.

    2) Can you suggest a set of freq config that works with x6 interpolation and serdes rates close to 12.5GHz with valid PLL frequency.

    Thank you!

  • 0 in reply to Daimeng Zhang
    TI__Genius 11940 points

    Hi Daimeng,

    The reason that you are getting invalid PLL frequency is because the VCO frequency is not within the VCO operating frequencies stated in the datasheet, PLL/VCO Electrical Characteristics Table. To fix this you will have to adjust the M and N ratio to get a valid PLL frequency. One configuration that is close to what you want is using M=5 and N=1, however this is at a lower serdes rate.

    Regards,

    David

  • 0 in reply to David Chaparro
    Prodigy 60 points

    Thank you David! I have one last related question:

    Why for # of serdes lanes per DAC = 2 lanes, the interpolation option doesn’t have x10? When it is 4 lanes, the interpolation has x10. What is the limiting factor for having 2 lanes and x10 interpolation?

    Thanks!

    Best,

    Daimeng

  • 0 in reply to Daimeng Zhang
    TI__Genius 11940 points

    Hi Daimeng,

    This limitation has to do with the internal clock dividers and logic blocks only being designed to support specific interpolation and JESD mode combinations. 

    The datasheet has a table that shows the combinations that are supported. It is Table 9: JESD204B Formats for DAC38RFxx in the datasheet, page 44.

    Regards,

    David Chaparro