All use CPHA = 0, CPOL = 0.
1. The issue is for description of datasheet.
Datasheet shows, the delay time , tD_CKDO , is 12ns, which is SCLK launch edge to (next) data valid on SDO-x.
The described in the datasheet shows, setting CPHA=0, CPOL=0, CLK launch edge is rising edge, but why the picture in the datasheet shows like CLK is falling edge?
Instead, the described in the datasheet shows , setting CPHA=0, CPOL=1, SCLK launch edge is falling edge, but why the picture in the datasheet shows like CLK is rising edge?
The question is which description is right, picture or narrative of document?
2.
In dual SDO mode, datasheet shows, SDO-0 pass to MSB, and then SDO-1 pass to MSB-1...., and go on. But in the actually test result is contrary.
Whether it is a negligence in control, or the chip action is different from the description?
3. Programming isuue:
I set vref x+/-2.5 (ie fit the time rule) and can’t get the correct data until repeat reading the translation time data about 4~5 times.
Has anyone happened to this situation, and how to fix it?
Thanks.