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ADS8661: Unexpected action and questions of datasheet description.

Part Number: ADS8661

All use CPHA = 0, CPOL = 0.

 

1. The issue is for description of datasheet.

Datasheet shows, the delay time , tD_CKDO , is 12ns, which is SCLK launch edge to (next) data valid on SDO-x.

The described in the datasheet shows, setting CPHA=0, CPOL=0, CLK launch edge is rising edge, but why the picture in the datasheet shows like CLK is falling edge?

Instead, the described in the datasheet shows , setting CPHA=0, CPOL=1, SCLK launch edge is falling edge, but why the picture in the datasheet shows like CLK is rising edge?

The question is which description is right, picture or narrative of document?

2.

In dual SDO mode, datasheet shows, SDO-0 pass to MSB, and then SDO-1 pass to MSB-1...., and go on. But in the actually test result is contrary.

Whether it is a negligence in control, or the chip action is different from the description?

3. Programming isuue:

I set vref x+/-2.5 (ie fit the time rule) and can’t get the correct data until repeat reading the translation time data about 4~5 times.

Has anyone happened to this situation, and how to fix it?

Thanks.

  • Hi user4927919,

    1. The ADS8661 datasheet only shows or describes the ADC's capture edge is the rising edge of SCLK for SPI-00 mode in table 8 and 9, can you please let me know where the datasheet describes "launch edge is rising edge" for SPI-00 mode?  

       Same question for SPI-01 mode, the ADS8661 datasheet only shows or describes the ADC's capture edge is the falling edge of SCLK for SPI-01 mode in table 8 and 9, can you please let me know where the datasheet describes "launch edge is falling edge" for SPI-01 mode?

    2. The datasheet is correct and the first bit from the SDO is always MSB. Can you please provide your timing plot including /CS,SCLK,SDI and SDO? also let me know your input voltage on the ADC input and the ADC input range you configured, I can check for you.

    3. What's your command to the ADC for configuring +/-2.5Vref input range? also, what's your command to read the register content? a timing plot captured by an oscilloscope will be very helpful.

    Best regards,

    Dale

  • 1.

    To put it another way, when CPOL = 0; CPHA = 0, tD_CKDO’s launch edge is rising or falling trigger?

    2.

    Input voltage is 3V, and range is +/-10.24V. Observed 163.5us, I think the actions of sdi_0 and sdi_1 are opposite to the description of datasheet.

    Can you check for me that is the action work right?

    3.

    CPOL = 0; CPHA = 0

    When set RESET and delay 20ms, change Vref to x +/-2.5.

    Input voltage is 3V.

    The output signal is transferred to the FPGA and processed into a 12-bit parallel data of BUS 1.

    We can see the data of FPGA after conversion is not stable in the first few cycles.

    Zoom in 9.94us. Output signal is 2’b1010_0110_0000(3.04V)

    After several readings, it can be found from about 33us on BUS1 is stable.

    At this time, we will go to see if the output data (43.8us) is the same as the beginning, and found the output is 2’b1010_0101_0000(2.96V). It can be verified that when programming changes the input range, the first few readings will be unstable.

    After programming the input range, order several NOP commands. We can find the data that become stable at the beginning (Bus1 data is 12’d264x ~ 265x).

  • Hi Ryan,

    1. The launch edge is the falling edge of SCLK for SPI-00 mode (CPOL= 0; CPHA= 0), the picture you showed clearly states the falling edge of SCLK.

    2. I believe the "sdi_0 and sdi_1" are actually MOSI for your controller, the ADS8661 ADC only has one SDI signal.

    I'm curious why you are sending only 7 SCLKs instead of 12 or 16 SCLKs to the ADC every time.

    • Also, is your sdi_0 shared with other device? I saw some signals before SCLKs are available.
    • Which signal is connected to the CONVST/CS pin of ADC? I saw you have both ss(J1-24) and start (J1-13) signals and I believe it's ss signal. Why is there an additional pulse after the normal pulse of 105ns width on your start signal in 2nd cycle? 
    • What's your SCLK frequency?

    The data on the sdi_0 or sdi_1 seems incorrect to change at the edge of SCLK, can you provide a zoom-in timing captured with an analog oscilloscope for just one cycle? a virtual oscilloscope can not show a real timing especially edge of clock.

    3. Your ADC conversion seems correct because your code is correct according to your input voltage, hence your timing should be correct, however I'm still interested in the questions above.

    Any commend to program internal registers will get executed at the rising edge of the CONVST/CS signal and it will take some time to settle, hence you can insert an additional CONVST signal at the arrow position shown below, then wait for some time to start the official conversion.

    Best regards,

    Dale

  • 1. Done.

    2-1.

    Q: I'm curious why you are sending only 7 SCLKs instead of 12 or 16 SCLKs to the ADC every time.

    A: When using dual SDI MODE, SDI single only exists in the first 6 clock cycle. I use 7 clock cycle to speed up conversion, last clock cycle is for FPGA input delay.

    2-2.

    Q: Which signal is connected to the CONVST/CS pin of ADC? I saw you have both ss(J1-24) and start (J1-13) signals and I believe it's ss signal. Why is there an additional pulse after the normal pulse of 105ns width on your start signal in 2nd cycle? 

    A: That’s right, ss is CONVST/CS pin of ADC;Start is just used to simulate the start signal to start the conversion. 105ns width pulse is 0’s result, parallel with sdi-0, but it has no reference value due to resolution is not good enough.

    2-3.

    Q: What's your SCLK frequency?

    A: 40Mhz by conversion, 20MHz by programming.

    2-4.

    Q: The data on the sdi_0 or sdi_1 seems incorrect to change at the edge of SCLK, can you provide a zoom-in timing captured with an analog oscilloscope for just one cycle? a virtual oscilloscope can not show a real timing especially edge of clock.

    A: 

    Yellow one is CONVST/CS, green is SCLK, blue is SDI-0, red one is SDI-1, input=3V , range=+/-10.24V

    Dual SDI mode

    Zoom in dual sdi mode


    Single SDI mode


     

    3.

    ADC conversion is correct, but unstable. Conversion result is 12’d2670 at the beginning, stable result is 12’d265X after 36us. All CONVST/CS commend programs after RVS is 1’b1, it means ADS8661 is settle completely.

    Besides, you says that the delay after programming is control by MCU, and RVS is high in the first conversion, it means ADS8661 is settle completely, but somehow result is uncorrect.

    Best regards,

    Ryan

  • 1. Done.

    2-1.

    Q: I'm curious why you are sending only 7 SCLKs instead of 12 or 16 SCLKs to the ADC every time.

    A: When using dual SDI MODE, SDI single only exists in the first 6 clock cycle. I use 7 clock cycle to speed up conversion, last clock cycle is for FPGA input delay.

    2-2.

    Q: Which signal is connected to the CONVST/CS pin of ADC? I saw you have both ss(J1-24) and start (J1-13) signals and I believe it's ss signal. Why is there an additional pulse after the normal pulse of 105ns width on your start signal in 2nd cycle? 

    A: That’s right, ss is CONVST/CS pin of ADC;Start is just used to simulate the start signal to start the conversion. 105ns width pulse is 0’s result, parallel with sdi-0, but it has no reference value due to resolution is not good enough.

    2-3.

    Q: What's your SCLK frequency?

    A: 40Mhz by conversion, 20MHz by programming.

    2-4.

    Q: The data on the sdi_0 or sdi_1 seems incorrect to change at the edge of SCLK, can you provide a zoom-in timing captured with an analog oscilloscope for just one cycle? a virtual oscilloscope can not show a real timing especially edge of clock.

    A: 

    Yellow one is CONVST/CS, green is SCLK, blue is SDI-0, red one is SDI-1, input=3V , range=+/-10.24V

    Dual SDI mode

    Zoom in dual sdi mode


    Single SDI mode


     

    3.

    ADC conversion is correct, but unstable. Conversion result is 12’d2670 at the beginning, stable result is 12’d265X after 36us. All CONVST/CS commend programs after RVS is 1’b1, it means ADS8661 is settle completely.

    Besides, you says that the delay after programming is control by MCU, and RVS is high in the first conversion, it means ADS8661 is settle completely, but somehow result is uncorrect.

    Best regards,

    Ryan

  • 1. Done.

    2-1.

    Q: I'm curious why you are sending only 7 SCLKs instead of 12 or 16 SCLKs to the ADC every time.

    A: When using dual SDI MODE, SDI single only exists in the first 6 clock cycle. I use 7 clock cycle to speed up conversion, last clock cycle is for FPGA input delay.

    2-2.

    Q: Which signal is connected to the CONVST/CS pin of ADC? I saw you have both ss(J1-24) and start (J1-13) signals and I believe it's ss signal. Why is there an additional pulse after the normal pulse of 105ns width on your start signal in 2nd cycle? 

    A: That’s right, ss is CONVST/CS pin of ADC;Start is just used to simulate the start signal to start the conversion. 105ns width pulse is 0’s result, parallel with sdi-0, but it has no reference value due to resolution is not good enough.

    2-3.

    Q: What's your SCLK frequency?

    A: 40Mhz by conversion, 20MHz by programming.

    2-4.

    Q: The data on the sdi_0 or sdi_1 seems incorrect to change at the edge of SCLK, can you provide a zoom-in timing captured with an analog oscilloscope for just one cycle? a virtual oscilloscope can not show a real timing especially edge of clock.

    A: 

    Yellow one is CONVST/CS, green is SCLK, blue is SDI-0, red one is SDI-1, input=3V , range=+/-10.24V

    Dual SDI mode

    Zoom in dual sdi mode

    Single SDI mode

    3.

    ADC conversion is correct, but unstable. Conversion result is 12’d2670 at the beginning, stable result is 12’d265X after 36us. All CONVST/CS commend programs after RVS is 1’b1, it means ADS8661 is settle completely.

    Besides, you says that the delay after programming is control by MCU, and RVS is high in the first conversion, it means ADS8661 is settle completely, but somehow result is uncorrect.

    Best regards,

    Ryan

  • Hi Ryan,

    Thanks for your details, however you posted same information three times.

    Can you please try SPI mode 1 ( CPHA = 0, CPOL = 1) to capture the data? I checked your timing and the falling edge should be more stable to capture the data for your controller, see the highlight in blue for single SDO timing and the highlight in red for dual SDO timing below:

    Best regards,

    Dale