Dear Sir
ADS54J69IRMP Device SPI Register map value generation GUI is Required sir
kindly provide link to download the same sir
thank you
regards
Balakrishna J
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Dear Sir
ADS54J69IRMP Device SPI Register map value generation GUI is Required sir
kindly provide link to download the same sir
thank you
regards
Balakrishna J
Dear Sir,
Thank you very much
Can you please help with FPGA Interface for the same
1) Linux SPI Driver or bare metal SPI Driver to interface with Xilinx MPSOC
2) confused with register sets generated from GUI, datasheets says some set of registers and GUI Generates some sets
so little confusion
i would like to operate ADC at 320MHz clock for sampling and 2 lane per channel , both channel needs to be active and
LMFS => F= 1 and K=1
please help out
thank you
regards
Balakrishna J
Balakrishna,
For #1, I cannot help with this.
For #2, per the JESD204B standard, the following equations must be meet: 17 < F * K < 1024 and 1 < K < 32
Since you will be using LMF = 422, F = 2. To meet the equations above, we normally set K = 16.
This part can operate in either low pass or high pass mode. I am sending configuration file for you to try that will be configured for low pass mode with K = 16.
With a sample rate of 320MHz, the ADC output rate will be 160MHz. SYSREF = ADC data rate / (n * K), with n = whole integer.
The maximum SYSREF frequency you can use is 160M / 16 = 10MHz.
Give this a try.
Regards,
Jim
0x0000 0x81 0x0011 0x80 0x0056 0x08 0x0039 0xC0 0x003A 0x40 0x0059 0x20 0x4004 0x68 0x4003 0x00 0x4002 0x00 0x4001 0x00 0x60F7 0x01 0x6041 0x12 0x604D 0x08 0x6052 0x80 0x6072 0x08 0x6000 0x01 0x6000 0x00 0x4004 0x69 0x4003 0x00 0x6000 0x80 0x6006 0x0F 0x6001 0x31 0x6031 0x0A 0x6032 0x0A 0x4004 0x6A 0x4003 0x00 0x6012 0x02 0x6016 0x00 0x4004 0x61 0x4003 0x00 0x6068 0x02