This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC8750: Which GND,(analog GND or digital GND) PCB pattern should be wider?

Part Number: DAC8750

 Hello guys,

 One of my customers is routing PCB pattern of their own board to evaluate DAC8750.

 But due to PCB space and routing issue, they can't route wide pattern for both of analog GND and digital GND.

 At this situation, they have 2 questions as the follows.

 Q1. Which GND,(analog GND or digital GND) PCB pattern should be wider?

 Q2. Is analog GND connected to digital GND internally?

 Could you please give me your apply?

 It would be much appreciated.

 Best regards,

 Kazuya. 

  

  • Hello Kazuya,

    The analog and digital GNDs are not directly connected internally but the ESD diodes between them will limit the potential difference between them. We recommend the use of a ground plane if possible with via connections to both grounds.

    If that is not feasible, I recommend keeping the trace routes short and wide enough to flow the max current through the ground with some tolerance. The analog gnd will have a max current of approx 35-40mA. The digital ground will have dynamic current flowing through when writing SPI however this current will be much smaller relative to the analog ground. 

    The analog and digital grounds have to be star connected together at some point near the DUT especially if separate traces are used for these grounds. 

    I hope that helps.

    Regards,

    Reza

  •  Hello Reza,

     Thank you very much for your reply.

     It is very helpful for the customer and me.

     Could I ask you an additional question as the follow? (They are cosidering whether DAC8750 is no problem or not in some irregular conditions as FMEA) 

     The customer worry that IOUT source current may become very big when IOUT is shorted to GND after IOUT terminal open condition (floating).

    Because T2 PMOSFET in Figure 53 on page 21 of DAC8750 datasheet shoud be full on when IOUT is open condition.

     They want to know whether the device is no problem (no damage) or not when IOUT is connected to GND after IOUT open condition.

     If the device is damage in the case, could you please tell me how to avoid the device damaging?

    Is a resistor needed to insert between DAC8750 IOUT terminal and connector or terminal block? 

     Thank you again and best regards,

     Kazuya.

  • Hello Kazuya,

    The DAC8750 is designed to operate under both IOUT open circuit and short circuit to ground conditions. When IOUT is open circuit, an IOUT fault alarm will be generated to notify the user of the fault. The device does not get damage regardless.

    When transitioning from an IOUT circuit to a short circuit under certain extreme cases, the absolute max IOUT-to-GND potential could be exceeded and this could damage the device. This is more likely to occur at higher AVDD voltage (36V) and when IOUT is shorted to GND through a very long cable that acts as series inductive load with a parallel capacitive load to ground. 

    The step response through such a load can produce over and under shoot voltages which could violate the abs max limits of the device. To avoid this, it is recommended to protect the current output using components that include a small series resistor in addition to some TVS & clamp diodes. Please refer to TIPD153 for the details of the protection circuit. 

    Thanks

    Reza

  •  Hello Reza,

     Do you have any recommended value for the small series resistor?

     Is one of recommended 15ohm which is used on EVM?

     Also is there any limitation of IOUT source current? For example, it must be less than 500mA...

     They think IOUT source current may become very big with short term (for example, 100us) when IOUT is shorted to GND

    after IOUT terminal open condition (floating) because IOUT internal constant current circuit should needs the short term

    to adjust IOUT current to the target current.

     Could you please give me your comment or advice?

     Thank you very much and best regards,

     Kazuya 

  • Hello Kazuya,

    I recommend using a 15ohm series resistor as shown in the EVM design. 

    Like you correctly said, the response time of the DAC to events including open-to-short circuit events is determined by the bandwidth of the DAC which is close to 1MHz. However, the max output current is limited by the gate potential of the output PMOS and R3 resistor between the output FET and the DAC supply such that IOUT absolutely cannot exceed 100mA under any normal transient operation and practically would not even exceed 24mA since the loop response is quite fast. 

    Regards,

    Reza

  •  Hello Reza,

     Thank you very much for your reply and I'm sorry to be late my response.

     Could I ask you an additional question as the below?

    Q. My customer use 24V for AVDD. I think the maximum current would be exceeded 100mA with 15ohm series

    when IOUT-GND become short condition after IOUT is open. Is it no problem?

     Thank you again and best regards,

     Kazuya.

       

     

  • Hello Kazuya,

    I want to clarify my earlier point. IOUT short circuit is a valid load condition and when it happens, the current will not exceed 24mA as it is regulated by a feedback loop. The 100mA max possible output is derived assuming that the feedback loop is not working and if that were to happen, then the max output current is defined by the supply voltage and what we refer to as R3 resistor. This is where the 100mA max number comes from.

    The DAC has been tested several times with open-to-short conditions and it has always worked fine so long as you have the 15ohm series resistance. The customer should not experience any issue at 24V AVDD. 

    Regards,

    Reza

  •  Hello Reza,

     I understood well what you said.

     Your comments are very helpful for the customer and me.

     Thank you very much and best regards,

     Kazuya.