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DAC38J84: DACCLK Review Request

Kazuki Itoh

Genius 9165 points

Part Number: DAC38J84

Hi team,

I am trying to generate an internal DACCLK with a frequency of 2211.84MHz with the PLL and VCO of the DAC38J84.
I input 122.88MHz externally. N divider=1 / Prescalar=2 /M divider=18, VCO Frequency = 4423.68MHz ( pll_vcosel = '1', pll_vco = '110010'(50), pll_vcoitune = '10 ').

DACCLK frequency should be set to 2211.84 MHz, correct?
Also, is there a frequency range that PFD can be compared to?I guess it depends on the CP value.

Best regards,

Itoh

over 3 years ago

0 Kang Hsia over 3 years ago

TI__Guru 66004 points

Itoh-san,

You may use prescaler of 4 along with the VCO setting of the following

The PFD rate has to match your external clock rate of 122.88MHz.

0 user5983069 over 3 years ago in reply to Kang Hsia

Intellectual 320 points

Mr. Kang,

I think that if I set Prescalor as 4 ,and VCO =4423.68MHz, DACCLK become 1105.9MHz(4423.68/4=1105.9MHz)

We want to make 2211.84MHz ,so try to set Prescalor 2 . Is this right?

and is it possible to insert for example 2211.84MHz to PFD? (for exapmle insert 2211.84MHz in DACCLKP/N pin and set N as 1)

Takeshi

0 Kang Hsia over 3 years ago in reply to user5983069

TI__Guru 66004 points

Takeshi-san,

user5983069 said:
We want to make 2211.84MHz ,so try to set Prescalor 2 . Is this right?

Yes, correct. Sorry for the mistake.

user5983069 said:
is it possible to insert for example 2211.84MHz to PFD? (for exapmle insert 2211.84MHz in DACCLKP/N pin and set N as 1)

You will need to increase the N value to keep the PFD running below 500MHz. PFD of 500MHz is max range for the on-chip PLL

-Kang

0 user5983069 over 3 years ago in reply to Kang Hsia

Intellectual 320 points

Mr.Kang,

Thank you very much for your answer.

I understood.

Takeshi