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ADS8866: 5 LSB's not changing

Part Number: ADS8866

I've been using the ads8866 in a project, making an initial prototype on a perf-board that worked well (or as well as could be expected with the noise of wires dangling everywhere). Everything seemed to be working, so I moved it onto a PC board. Now using the same software (pinout, timing and everything) I initially soldered on an ADC and it didn't work at all. On the scope the DOUT pin started 3V and dropped to zero instantly and stayed there. I figured it may have been broken while installing, since I soldered it on by hand. Took the old one off, put on a new one with a little more care and got some data back this time. However, after closer inspection, I realized that the 3 least significant bits are always 0. The rest of the bits seem to be flipping with increasing load, just not the last 3.

Is this due to poor soldering technique, or could there be some other issue that can lead to missing bits? How fragile are these things to the heat of a soldering iron? Should we even attempt to solder these by hand?

  • Hello James,

    Welcome to the TI E2E Community.

    The behavior that you observe could be due to a slightly damaged device, where the LSB's no longer work.  This could also be due to marginal timing issues that worked on the first part you used, and now, on a different device, do not.

    If possible, please capture the waveforms on the IO pins, DIN, DOUT, SCLK, CONVST, and attach them to this post.

    Thank you!

    Regards,

    Keith Nicholas
    Precision ADC Applications

  • I scoped it out a little bit after sending the initial question, and one thing a partner brought up is there is a slight gap between the 8-bit spi transfers (8-bit, slight pause, then next 8-bits). Would that cause issues with this converter? It looks suspiciously like a 5 clock cycle gap between the two bursts.

    If that doesn't sound like an issue I can scope it out again and send pictures, but its a pain because we don't have great test points and our scope only has 2 channels. 

  • Here's an example, I slowed down the SPI clock to 120 kHz blue is clock and yellow is dout on ADC. We are etting last 5 bits 11000 every time.

  • Hello James,

    There is no problem with a time gap between the two 8b transfers.  Are you using DIN as Chip Select, or do you have this pin tied high for 3-wire SPI operation?

    The output data relative to SCLK looks correct.  Can you send a similar picture with CONVST and SCLK?  What is the input voltage (and reference voltage) for the above waveform?

    The ADS8866 starts the conversion on the rising edge of CONVST, and you must wait at least 8.8uS before starting SCLK to retrieve the data.  If not, this could show corrupted data.

    Regards,
    Keith

  • DIN is tied high. Input voltage is 1.533V,  reference is 3.026V. VDD and AVDD are 3.256V

    I've uploaded a drive link, couldn't upload all the pics to this forum.

    https://drive.google.com/drive/folders/19dCf34eaEsbP4s-GRaYm3--5EkWZrpiq?usp=sharing 

    In all pictures the yellow is CONVST

    the pictures are named after the blue input, with multiple pictures for perspective. I noticed the SCLK is just barely 8us after falling edge of convst. I've fixed that (picture not included, but you can take my word for it), I added no-ops before and after running SCLK, there's a healthy 10us gap between the convst falling edge and the first rising SCLK as well as 10us "quiet time" as it is referred to on the data sheet. I don't think the issue is timing unless I'm missing something. 

    https://drive.google.com/drive/folders/1OngGdbZXsUxumnqEGGTfmeBf5Zy6ai7g?usp=sharing

    This is the analog circuitry for the application. U4 is actually a OP297G, its just a precision dual op-amp. The AD620 and OP297 are both very low-impedance outputs. Is there anything blatantly wrong with this that you notice?

    Some discrepancies from the datasheets recommendations in DAQ 10.2.2 on datasheet that we're conscious of:

    1. We're not using one of the special "precision reference" ICs.

    2. There's no 10uF cap on the REF pin.

    3. AVDD DVDD and DIN are all tied together to a 3.3V regulator output, decoupled as shown in U5 rather than each power pin being separately decoupled.

  • Hello James,

    I looked at your timing waveforms.  As long as you have 10uS delay between CONVST falling edge and first SCLK rising edge, as well as 10uS between the last SCLK falling edge and the rising edge of CONVST, you should not have any timing issues.

    Your output code is not too far off, but no where near 16b performance.  The reference pin must have a low impedance source driving it, with several uF of capacitance.  This may be causing what you see.  If the reference droops too much in voltage at the REF input pin of the ADC, the last 4-5 bits could be corrupted.  At a minimum, I would try adding a 10uF ceramic cap between the REF and GND pins of the ADS8866.

    AVDD and DVDD should have separate decoupling capacitors for best performance, but I do not think this is causing the behavior that you are reporting.

    Unfortunately, I was not able to view your schematics, so I am basing my comments on your above description.

    Thanks,
    Keith

  • Adding a 10uF cap on the reference definitely helped.  We've got all the bits flipping at least and with a little filtering looks like good data. Thank you very much!

    P.S. Would it be a good idea to rename this thread to "5 LSBs not changing" or something along those lines in case someone makes the same mistake I did?

  • Hi James,

    Glad to hear this fixed your problem.

    Good idea on changing the title; should be more useful description for searching.

    Regards,
    Keith