• Resolved

DAC38J84: DAC Alarms at High Speed

Prodigy 180 points

Replies: 1

Views: 58

Part Number: DAC38J84

Hi


We are having an issue with the DAC38J84.

FPGA                   ---  Virtex 7
Clock Generator  ---  LMK04826
DAC                     ---  DAC38J84

In the DAC34J84, there are some Error / Alarm indications


a. 8b/10b Disparity error
b. 8b/10b Not in table code error
c. Code Synchronization error
d. Elastic Buffer Overflow error
e. Link Configuration error
f.  Frame Alignment error
g. Multiframe Alignment error
h. FIFO Full
i.  FIFO Empty

 

We are configuring DAC in two modes

1. At Low Speed 312.5 MSPS Sampling rate.
2. At High Speed 2.5 GSPS Sampling rate.

Case 1 : Low Speed

SERDES Rate                       = 6.25 Gbps
LMK Clk Frequency to FPGA   = 156.25 MHz (SERDES Rate / 40)
LMK Clk Frequency to DAC    = 312.50 MHz
SYSREF Frequency               = 4.8828125 MHz (FPGA Clk / 64)
Interpolation                       = x 1
Output Data from DAC         = Singletone 25 MHz

 

We are measuring the clock coming to FPGA and DAC. They are as per specs.
At low Speed, we are able to capture the correct data from DAC.
JESD Link up is done and there are NO ALARMS in DAC.

Case 2 : High Speed

SERDES Rate                      = 6.25 Gbps
LMK Clk Frequency to FPGA  = 156.25 MHz (SERDES Rate / 40)
LMK Clk Frequency to DAC   = 2.5 GHz
SYSREF Frequency              = 4.8828125 MHz (FPGA Clk / 64)
Interpolation                      = x 8
Output Data from DAC        = Singletone 25 MHz

 

We are measuring the clock coming to FPGA and DAC. They are as per specs.
At High Speed, we are unable to capture the correct data from DAC.
JESD Sync Signal is continuously toggling and there are ALARMS in DAC.

 

We are getting the following ALARM / Error indications at High Speed
a. 8b/10b Disparity error
b. 8b/10b Not in table code error
c. Code Synchronization error
d. Elastic Buffer Overflow error
e. Frame Alignment error
f. Multiframe Alignment error
g. FIFO Full
h. FIFO Empty

 

These errors indicate that there is problem with JESD Link up at high speed.

It would be helpful if you guide us to resolve this issue

Please Find Attachments :

1. LMK Configuration files at Low and High speeds
2. DAC Configuration files at Low and High Speeds
3. DAC Outputs at Low speed

8231.LMK1_LOW_SPEED.txt

5516.LMK1_HI_SPEED.txt

DAC_configurations_Low_speed.txt

DAC_configurations_High_speed.txt

Thank You

  • Hi Pavan,

    The first issue at hand is the SerDes FIFO error. This means the rate coming from the Virtex 7 is not matching the 6.25Gbps that is required. I noticed the LMK setting between the low and high speed are different. In theory, the FPGA clock and SYSREF clock should remain the same, if you are using the DAC38J84 EVM. Please double check the settings as they may be incorrect. Please confirm if you are using EVM or some other PCB board that you have designed. 

    Thanks.