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DAC161S997: DAC161S997 of Respons time,Updata rate

Part Number: DAC161S997

Hellow

Model:DAC161S997

1.I want to know the response time of current Loop

   I have confirmed in the data sheet that the settling time changes depending on the capacity.

   I think the response time will change depending on capacity.

   I want to define the change time for current loop from 10% - 90%

2.Is there a maximum output update rate to maintain 4mA current?

   Even if the data is continuously updated at 10MHz clock, is the supply current very low?

Please give me advice.

  • Hello,

    1. You are right that the settling time will change based on capacitors C1, C2, & C3. Figure 4 of the datasheet shows the typical settling time for the DAC for different steps under different cap values. The DAC settling is dominated by the slew rate from 10% - 90%, hence you can expect similar response times to the data in figure 4. 

    2. By default, a SPI timeout error will occur after 100ms of no valid activity on the SPI bus. Such an error will drive ERRB low and subsequently cause the loop current to change to its error low (if errlvl is tied to gnd) or error high (if errlvl is tied to VD). The current levels corresponding to error low/ high can be set using their corresponding registers.

    This behavior can be disabled by masking SPI timeout errors by writing '1' to bit 0 of the ERR_CONFIG register. 

    Let me know if that helps. Thanks!

    Regards,

    Reza 

  • Thank you for answer.

    I understand that the DAC requires continuous inputs

    Best regards,