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DAC38J84: MULTI DAC SYNCHRONIZATION

Part Number: DAC38J84

HELLO,

config_file.rarIn our custom board we are having 2 LMK(lmk04826B) and 3 DAC(DAC38J84) are connected to each LMK.
We are configuring LMK in zero delay mode and DAC with 312.5 MHz inputrate and interpolation of eight.

problem:
Initialy we tried to synchronize 3 DAC of LMk1,synchronization was happening.
then we tried to synchronize 3 dac of LMK2 , we could achieved synchronization.
when we combined to synchronization all 6 DAC

1) JESD IS NOT LOCKING  FOR ALL DACs ,its random.

2) we are getting alarms on DACs.

note : One of lmk1 output(100MHz) is feed as lmk2 input.

could you please help me with this?

I HAV ATTACHED MY CONFIGURATION FILE FOR REFERNECE

THANK YOU.

  • User,

    I cannot open the config file. I do not know what a .rar file is. Please send this as word or notepad format.

    What LMF setting are you using for the DAC's?

    What is the rate of the DAC clock?

    Are you using the DAC PLL? If so, what are the settings?

    What is the LMK refence clock and what input pins is it connected to? Is this signal routed using the same length to both LMK's?

    Can you verify if the LMK output clocks are synchronized?

    Is the DAC CLK and SYSREF routed the same length to all DAC's?

    What is the SYSREF frequency?

    Can you get an output from all DAC's using NCO only mode? This will verify clocks, SPI and power are correct.

    What value is K and RBD?

    Are you issuing a hard reset to all DAC's after power and clocks are provided?

    What alarms are you getting?

    Can you send your schematic?

    Regards,

    Jim

  •  Hello jim,

    i am attaching  the file as per your suggestions.

    What LMF setting are you using for the DAC's?

    442

    What is the rate of the DAC clock?

    2500MHz

    Are you using the DAC PLL? If so, what are the settings?

    we are not using DAC PLL

    What is the LMK refence clock and what input pins is it connected to? Is this signal routed using the same length to both LMK's?

    LMK REF IS 100MHz connect to OScin. yes the signal are length  matched

    Can you verify if the LMK output clocks are synchronized?

    yes, clock are synchronized.

    Is the DAC CLK and SYSREF routed the same length to all DAC's?

    YES.

    What is the SYSREF frequency?

     4.88 MHz

    Can you get an output from all DAC's using NCO only mode? This will verify clocks, SPI and power are correct.

    YES, all dacs are working fine and  are getting sychronized w.r.t each LMK.

    What value is K and RBD?

    k 31 and  RBD 15

    Are you issuing a hard reset to all DAC's after power and clocks are provided?

    NO

    What alarms are you getting?

    Multiframe and link config error and FIFO errors.

     

     

  • dac_config1.txt
    0x0    0x0 
    0x0    0x1 
    0x0    0x218
    0x1    0x03
    0x2    0x2082
    0x3    0xA300
    0x4    0xF0F0
    0x5    0xFF07
    0x6    0xFFFF
    0x7    0x3100
    0x8    0x0
    0x9    0x0
    0xA    0x0
    0xB    0x0
    0xC    0x400
    0xD    0x400
    0xE    0x400
    0xF    0x400
    0x10   0x0
    0x11   0x0
    0x12   0x0
    0x13   0x0
    0x14   0x0
    0x15   0x0
    0x16   0x0
    0x17   0x0
    0x18   0x0
    0x19   0x0
    0x1A   0x20
    0x1B   0x0
    0x1E   0x9999
    0x1F   0x9980
    0x20   0x8008
    0x22   0x1B1B
    0x23   0x1FF
    0x24   0x10
    0x25   0x4000
    0x26   0x0
    0x2D   0x1
    0x2E   0xFFFF
    0x2F   0x4
    0x30   0x0
    0x31   0x1000
    0x32   0x0
    0x33   0x0
    0x34   0x0
    0x3B   0x1800
    0x3C   0x228
    0x3D   0x88
    0x3E   0x108
    0x3F   0x0
    0x46   0x1882
    0x47   0x1C8
    0x48   0x3143
    0x49   0x0
    0x4A   0xF1E
    0x4B   0xF01
    0x4C   0x1F03
    0x4D   0x300
    0x4E   0xF0F
    0x4F   0x1C61
    0x50   0x0
    0x51   0xDC
    0x52   0xFF
    0x53   0x0
    0x54   0xFC
    0x55   0xFF
    0x56   0x0
    0x57   0xFF
    0x58   0xFF
    0x59   0x0
    0x5A   0xFF
    0x5B   0xFF
    0x5C   0x1133
    0x5E   0x0
    0x5F   0x3210
    0x60   0x5764
    0x61   0x211
    0x64   0x1
    0x65   0x1
    0x66   0x1
    0x67   0x1
    0x68   0x7709
    0x69   0x0
    0x6A   0x0
    0x6B   0xBD07
    0x6C   0x7
    0x6D   0x90
    0x6E   0x0
    0x6F   0x0
    0x70   0x0
    0x71   0x0
    0x72   0x0
    0x73   0x0
    0x74   0x0
    0x75   0x0
    0x76   0x0
    0x77   0x0
    0x78   0x0
    0x79   0x0
    0x7A   0x0
    0x7B   0x0
    0x7C   0x0
    0x7D   0x0
    0x3B   0x1800
    0x25   0x6000
    0x3C   0x228
    0x3C   0x28
    0x3E   0x128
    0x4C   0x903
    0x4D   0x300
    0x4B   0x801
    0x4D   0x300
    0x4E   0xF0F
    0x0    0x418
    LMK1_HI_SPEED_0_delay.txt
    R0 (INIT)	0x000090
    R0	0x000010
    R2	0x000200
    R3	0x000306
    R4	0x0004D0
    R5	0x00055B
    R6	0x000600
    R12	0x000C51
    R13	0x000D04
    R256	0x010001
    R257	0x010155
    R258	0x010255
    R259	0x010301
    R260	0x010422
    R261	0x010500
    R262	0x0106F0
    R263	0x010755
    R264	0x010801
    R265	0x010955
    R266	0x010A55
    R267	0x010B01
    R268	0x010C22
    R269	0x010D00
    R270	0x010EF0
    R271	0x010F55
    R272	0x011001
    R273	0x011155
    R274	0x011255
    R275	0x011301
    R276	0x011422
    R277	0x011500
    R278	0x0116F0
    R279	0x011755
    R280	0x011810
    R281	0x011955
    R282	0x011A55
    R283	0x011B01
    R284	0x011C22
    R285	0x011D00
    R286	0x011EF0
    R287	0x011F11
    R288	0x012010
    R289	0x012155
    R290	0x012255
    R291	0x012301
    R292	0x012422
    R293	0x012500
    R294	0x0126F0
    R295	0x012711
    R296	0x012810
    R297	0x012955
    R298	0x012A55
    R299	0x012B01
    R300	0x012C22
    R301	0x012D00
    R302	0x012EF0
    R303	0x012F11
    R304	0x013019
    R305	0x013155
    R306	0x013255
    R307	0x013301
    R308	0x013402
    R309	0x013500
    R310	0x0136F1
    R311	0x013701
    R312	0x013820
    R313	0x013903
    R314	0x013A02
    R315	0x013B00
    R316	0x013C00
    R317	0x013D08
    R318	0x013E03
    R319	0x013F11
    R320	0x01408B
    R321	0x014100
    R322	0x014200
    R323	0x014311
    R324	0x0144FF
    R325	0x01457F
    R326	0x014618
    R327	0x01471A
    R328	0x014802
    R329	0x014942
    R330	0x014A02
    R331	0x014B16
    R332	0x014C00
    R333	0x014D00
    R334	0x014EC0
    R335	0x014F7F
    R336	0x015003
    R337	0x015102
    R338	0x015200
    R339	0x015300
    R340	0x015478
    R341	0x015500
    R342	0x015678
    R343	0x015700
    R344	0x015896
    R345	0x015900
    R346	0x015A78
    R347	0x015BD4
    R348	0x015C20
    R349	0x015D00
    R350	0x015E00
    R351	0x015F0B
    R352	0x016000
    R353	0x016110
    R354	0x0162A4
    R355	0x016300
    R356	0x016400
    R357	0x016550
    R369	0x0171AA
    R370	0x017202
    R380	0x017C18
    R381	0x017D77
    R358	0x016600
    R359	0x016700
    R360	0x016819
    R361	0x016959
    R362	0x016A20
    R363	0x016B00
    R364	0x016C00
    R365	0x016D00
    R366	0x016E13
    R371	0x017300
    R8189	0x1FFD00
    R8190	0x1FFE00
    R8191	0x1FFF53
    
    LMK2_HI_SPEED_0_delay.txt
    R0 (INIT)	0x000090
    R0	0x000010
    R2	0x000200
    R3	0x000306
    R4	0x0004D0
    R5	0x00055B
    R6	0x000600
    R12	0x000C51
    R13	0x000D04
    R256	0x010001
    R257	0x010155
    R258	0x010255
    R259	0x010301
    R260	0x010422
    R261	0x010500
    R262	0x0106F0
    R263	0x010755
    R264	0x010801
    R265	0x010955
    R266	0x010A55
    R267	0x010B01
    R268	0x010C22
    R269	0x010D00
    R270	0x010EF0
    R271	0x010F55
    R272	0x011001
    R273	0x011155
    R274	0x011255
    R275	0x011301
    R276	0x011422
    R277	0x011500
    R278	0x0116F0
    R279	0x011755
    R280	0x011810
    R281	0x011955
    R282	0x011A55
    R283	0x011B01
    R284	0x011C22
    R285	0x011D00
    R286	0x011EF0
    R287	0x011F11
    R288	0x012010
    R289	0x012155
    R290	0x012255
    R291	0x012301
    R292	0x012422
    R293	0x012500
    R294	0x0126F0
    R295	0x012711
    R296	0x012810
    R297	0x012955
    R298	0x012A55
    R299	0x012B01
    R300	0x012C22
    R301	0x012D00
    R302	0x012EF0
    R303	0x012F11
    R304	0x013019
    R305	0x013155
    R306	0x013255
    R307	0x013301
    R308	0x013402
    R309	0x013500
    R310	0x0136F9
    R311	0x013700
    R312	0x013820
    R313	0x013903
    R314	0x013A02
    R315	0x013B00
    R316	0x013C00
    R317	0x013D08
    R318	0x013E03
    R319	0x013F11
    R320	0x01408B
    R321	0x014100
    R322	0x014200
    R323	0x014311
    R324	0x0144FF
    R325	0x01457F
    R326	0x014618
    R327	0x01471A
    R328	0x014802
    R329	0x014942
    R330	0x014A02
    R331	0x014B16
    R332	0x014C00
    R333	0x014D00
    R334	0x014EC0
    R335	0x014F7F
    R336	0x015003
    R337	0x015102
    R338	0x015200
    R339	0x015300
    R340	0x015478
    R341	0x015500
    R342	0x015678
    R343	0x015700
    R344	0x015896
    R345	0x015900
    R346	0x015A78
    R347	0x015BD4
    R348	0x015C20
    R349	0x015D00
    R350	0x015E00
    R351	0x015F0B
    R352	0x016000
    R353	0x016110
    R354	0x0162A4
    R355	0x016300
    R356	0x016400
    R357	0x016550
    R369	0x0171AA
    R370	0x017202
    R380	0x017C18
    R381	0x017D77
    R358	0x016600
    R359	0x016700
    R360	0x016819
    R361	0x016959
    R362	0x016A20
    R363	0x016B00
    R364	0x016C00
    R365	0x016D00
    R366	0x016E13
    R371	0x017300
    R8189	0x1FFD00
    R8190	0x1FFE00
    R8191	0x1FFF53
    

    hello jim,

    please find the attachments.

    thank you

  • User,

    You must issue a hard reset otherwise some registers may not get configured properly.

    Regards,

    Jim

  • Hello Jim,

    thanks for your reply.

    what do we mean by hard reset ?  is it configuring  0x4a register, if so then i am issuing hard reset.

    my configuration flow is

    1.  LMK CONFIGURATION

    2. DAC CONDIFURATION

    3. CONFIGURIUNG jesd TX iP

    4. JESD TX IP RESET

    5. DATA TO DAC

    6. DAC HARD RESET

    then clearing alarms and reading them.

    with this flow i am getting alarms as mention in our prevoius conversation

    thanks

  • Toggle pin K8 (RESTB) low then high to issue a hard reset. This is not the same as toggling the soft reset register bit.

  • Hello jim,

     in my schematics this pin is left open.

    does toggling  0x2 reg 0th bit low to high is similar to hard rest.??

    if not please provide the alternate solution.

    thanks

  • User,

    I do not know if there is an alternate solution to the rest issue. I am looking into this. I did find an issue with your SYSREF frequency though.

    SYSREF rate  = data rate / (K * N)   where N is a whole integer.

    You mention a data rate of 312.5Msps and a K of 32. Your max SYSREF rate = 9.765625.

    If you are using a SYSREF of 4.88Msps, N cannot be a whole integer in the equation above. Change this frequency to this value or a divided by a whole integer if you want to run at a lower rate.

    Regards,

    Jim

  • HELLO JIM,

    sorry, it was a typo error.

    my sysref frequnecy is 4.8828125MHz  and N is a whole integer which can be found in the config file which i have sent you.

    Thanks

  • User,

    Using a software reset should be OK as the data sheet does mention you can leave the external reset pin floating.Your first step should be to get the DAC's connected to a single LMK working fine. After this, then I would attempt to synchronize the two LMK parts. I had no trouble getting a DAC setup working with your configuration. You may want to compare your register settings to the one attached. You will receive errors on the unused lanes.

    You may want to consult with the high speed clocking group regarding issues with synchronizing two LMK's.

    Your configuration flow should be as follows:

    1.  LMK CONFIGURATION

    2. Software DAC Reset

    3. DAC CONDIFURATION

    4. CONFIGURIUNG jesd TX iP

    5. JESD TX IP RESET

    6. DATA TO DAC

    7. DAC JESD Reset. Write the following data, in this order to address 0x4A:  0x0F00, 0x0F1E, 0x0F1F and 0x0F01 to reset the DAC JESD core. 

    Make sure SYSREF is running during steps 4-7

    Regards,

    Jim

    Fs_2500_LMF_442_K_32_8x_Int.cfg

  • Hello Jim

    thanks for your earliest reply and the configuration file.

    As i have mention in the beginning that my custom board has 3 DAC's connected to each LMK.

    all the DAC's are working with no alarms and i have acheived synchronization of 3 DACs connected to each LMK.

    but when i configure 6 dacs and 2 lmk .

    1.I am getting alarms continously(Multiframe and link config error and FIFO errors).

    2. my sync is toggling and because of this JESD is not locking

    Thanks

  • User,

    Please post this issue on the high speed clock forum. They are the LMK experts.

    Regards,

    Jim