DDC112: Input Current Measurement Errors above 50% Full Scale Current

Hi Brody,

Reading through the first part of your email, I understand that you are using larger feedback capacitors than the datasheet 250pF number but as you said, this could be ok, based on the app note you mentioned. The app note doesn't give a great explanation of conditions and limits but I am not sure that is your problem here, anyhow. The impression I get from the app note is that this is more about resetting the capacitor fast enough, so, probably any issues would result on missed specs (gradual degradation) but not catastrophic functionality fail. I.e., all this is to say that I would agree with you that you are likely to be ok there or at least this should not be related to the 2nd paragraph observations.

On that sense, the part I don't get in that paragraph is that somehow you mention putting 50% more current than the limits you describe? Say 6uA in the ~4uA setting (1000pF)? Is that right? I mean, in that case obviously the integrator output would hit the rail. I.e., at around 4/6th of your integration period the integrator will be full, the close loop will not work anymore (saturated) and your input will start rising as the current would keep flowing into the cap but the other side of the cap (at the output) is fixed. This is explained also on that same app note when talking about having the same cap for A and B (see PS). Did I get your 50% right or am I missing something? Or somehow you are saying that you are putting 4uA with the current source but the device is taking 6uA? Not sure how that would be, but anyhow, can you please confirm?

Thank you!
Edu

PS.: That explanation is in a different context but the same applies here. Notice that the explanation is assuming that max current during A and B is the same. If it was different I think you could actually use two different caps (although other secondary issues could surface due to mismatches).

Hi Eduardo, Thank you for your explanation, however your assumption is incorrect. What I meant by my issue is I can provide 2uA (max is 3.8uA) to the 1000pF, and that is where the chip starts saying it is seeing ~2.2uA. For the 470pF cap, I provide 1uA (max 1.8uA) and it reads that there is ~1.15uA coming in instead. The errors start to arrive whenever the input current is greater than 50% of the expected Full Scale Current. Does this make more sense? Best, -Brody

Ah! I see. Now I understand... You mean the DDC is reporting more than what the source says is putting... but not saturating. I bet the degradation is gradual? I mean, at 50% looks good but maybe it is already a bit off (higher) and then the error grows with input?

Also, you mention some ramping voltage at the input pin but not sure I got that. Can you describe how it looks over time vs CONV? I have not probed those devices myself (so, not sure if possible without affecting the operation), but can you check also the output? It would be interesting to see if it fully resets.

Regards,

Edu

The error actually shoots up dramatically at the 50% Full Scale Current number. The error below 50% full scale current is around 0.1%, but then once we break the 50% threshold, it shoots up to around 10-15%. I can attempt to do some probing later hopefully, but figured I would provide this info for now.

Also, the ramp up at the input appears to get cut off at 500 mV.

Hi Brody,

Yeah, that 500mV is very much what I would expect. The input ESDs end-up clipping the voltage and sink to ground the extra current. So, basically if the issue is an excess of current, when you look at the input you should see the voltage starting at zero right after the CONV edge and then climbing till it hits the ~500mV.  The point at which it starts climbing would tell you when the output is saturated. It would show that more current than one thinks, is going into the DDC. I've seen this happen before... Nevertheless, I can't figure what is going on here as your output is not saturated. The DDC is reporting ~60% of FSR.

The other thought (which I don't know, just guessing from the app note explanation) is that the device can't reset the feedback cap all the way. I think it would be hard to see any difference looking at the input node (it would start still from zero and start climbing at one point, similar to the previous case). But you should see it at the output node, with the voltage starting right after the CONV at the wrong value (because of a partial reset) and then climbing to saturation. Just a guess... Again in this case, this does not match what you are seeing because you are not seeing the output saturating, right? 

So, can't figure how the feedback loop of the amplifier stops working if the amplifier is not saturated. Please confirm the input/output waveforms and will run it by a designer...

Thank you!
Edu

Hi Edu,

Thank you for your continued work with me on this. I have attached two images below for reference. Please have a look. This is the best I can do right now as I have to request to get these taken for me while I work from home. Please let me know if you can gather anything from these scope traces, or if you would like to see more data in some way.

In image 1, the input current is under that previously discussed 50% Full Scale Current, so we don't see any ramp on the input, and also the output is producing the correct current measurment.

In image 2, the input current is above the 50% Full Scale Current value, and we then see a ramp up on the input, and the output is producing values that are HIGHER than the input current actually is.

Image 1: No ramp up on input voltage seen (Channel 2 - Reading IN1 pin; Channel 1 - Showing CONV trace)

Image 2: Ramp up on input voltage seen (Channel 2 - Reading IN1 pin; Channel 1 - Showing CONV trace)

Hi Brody,

No issue at all! Was just closing loose ends :)

So, we know the reason... Hope you can find a re-design that meets the targets. Feel free to PM me if you need help...

Best regards,
Edu