Other Parts Discussed in Thread: LMK04828, LMX2594
Hi,
We are using ADC12DJ5200RF in our design.
Does length matching required for output lanes? Like between the pairs which are operating on JESD204 interface.
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Hi,
We are using ADC12DJ5200RF in our design.
Does length matching required for output lanes? Like between the pairs which are operating on JESD204 interface.
Hi Anand,
No you don't have length match the sysref device clock with each other.
Regards,
Neeraj
Hi Neeraj,
As i checked in JESD204C document, we should length match between sysref and device clock if i am not wrong.
Please check again and let me know.
Regards
Anand B
Hi Anand,
You don't have to length match the device clock and sysref to the device. If you check the EVM for ADC12DJ5200RF you can see our Device clock is coming from LMX2594 device and sysref can either come from LMX2594 or LMK04828 device. So you don't have to length match them but the sysref clock and device should either come from the some clock source or should be derived from the same source.
You will only need to length match the Sysref and device clock if you are trying to synchronize multiple devices with each other and want to simultaneously sample at the same instant.
Regards,
Neeraj
Hi Neeraj,
Thank you for the reply.
We are using multiple devices and to be synchronized with each other. In this case what will be the length matching constraint?
Regards
Anand B
Hi Anand,
In general you want to be within half a clock cycle you device clock in terms of maximum mismatch. For example if your sampling clock is 5GHz your time period is 200ps so you want the max mismatch to be less than 100ps.
Regards,
Neeraj