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ADC3424: Test Pattern Confusion
Part Number: ADC3424
I am having identical issues to those outlined in the 'Test Pattern Confusion' thread that this post references.
I am running an ADC3424 at 40 MSPS, resetting it on power-up, enabling two wire mode, enabling test mode, and putting various test patterns out of the different channels. I have found the All 0s, All 1s, toggle pattern, custom pattern, and deskew pattern to work perfectly.
For the ramp mode, 0x44 in registers 0x0A and 0x0B, each step in the ramp is repeating 4 times - e.g. 0000111122223333 instead of the expected 0123 etc.
For the sine mode, 0x99 in registers 0x0A and 0x0B, I expect a repeating 8-point wave of 0, 599, 2048, 3496, 4095, 3496, 2048, and 599 as in the data sheet. In 12 bit data, this means it must be processed as unsigned for a maximum of 4095. I receive a repeating 8-point signal, however processed as unsigned, it returns 2711, 3117, 0, 978, 1384, 978, 0, 3117, way off. And when processed as signed 2's complement, I get 0, 978, 1384, 978, 0, -979, -1385, -979. This is a sine wave of the correct shape, but offset to 0 and scaled down.
Additionally, I noted that in the data sheet for the ADC3424, there may be an error in the Serial Register Description, specifically between pages 5 & 6. They describe bits required to output the different test patterns in registers 0x0A (chA & B), and 0x0B (chC & D). However, they report different bits for the custom, deskew, PRBS, and sine wave patterns - e.g. pg 55 states 0x0A = 0x55 is custom pattern, but pg 56 states 0x0B = 0x66 is custom pattern. Through testing, it appears that only pg55, register 0x0A is correct for all four channels. Any help or advice would be much appreciated!
We will investigate the ramp mode situation. --RJH
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In reply to RJ Hopper:
Please reference the following post:
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