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DDC232: Signals Required for Cascading Converters

Saad Shaikh1
Prodigy 30 points
Part Number: DDC232
Other Parts Discussed in Thread: DDC264EVM

Hi there,

My research group is currently working on a custom circuit board to house a DDC232 and measure the input of photodiodes. So far, we've had a prototype circuit board made and can successfully operate the DDC232 using an FPGA. We are now looking to produce further circuit boards and daisy-chain them together and I wanted to confirm which signals are required to do so.

Consider the case where we only add one additional DDC232 (2 boards in total), where the FPGA provides CLK, CLK_CFG, DIN_CFG, CONV, DCLK, RESET to the first DDC232 and receives DOUT and DVALID from the same DDC232. The DDC232 datasheet (pg. 21) suggests we would only need to connect DOUT of the second board to DIN of the first and also supply the second board with DCLK. Can you confirm that this is the case?

Here are the subsequent questions we have about the datasheet guidelines:

  1. How does the daisy-chained module receive configuration input (and its associated clock)? Does configuration of the second board happen at the same time of the first?
  2. How does the daisy-chained module receive other signals like CLK, CONV and RESET to control integration and DVALID generation for that chip?
  3. When the DDC232 connected to the FPGA outputs DVALID – what does that mean for the other DDC232? The datasheet does not appear to show how DVALID is cascaded across converters. I would suspect that a DVALID means that both DDC232s are ready to send data?
  4. Are the outputs of the configuration read-back and measurement readout cycle ordered automatically? That is, the output of the DDC232 connected to FPGA is then followed by the output of the daisy-chained module (or the other way round).

Of course, we will adjust the FPGA generation of DCLK to expect the correct amount of bits in readouts when adding more DDC232s.

Please let me know if you need any further information to answer my question. Any help is greatly appreciated.

Many thanks,

Saad

  • 0
    TI__Genius 11550 points

    Hi Saad,

    Please see my comment for your questions in GREEN below. I hope this answer all of your questions regarding using the device in daisy-chain mode. Thanks.

    -TC

    Consider the case where we only add one additional DDC232 (2 boards in total), where the FPGA provides CLK, CLK_CFG, DIN_CFG, CONV, DCLK, RESET to the first DDC232 and receives DOUT and DVALID from the same DDC232. The DDC232 datasheet (pg. 21) suggests we would only need to connect DOUT of the second board to DIN of the first and also supply the second board with DCLK. Can you confirm that this is the case?

    >> For Daisy-chain configuration, the first board DIN_1 is grounded or connected to other digital input and DOUT_1 is connected to the DIN_2 of the 2nd board. The daisy-chain data output can be retrieved from DOUT_2 signal. Please refer to the DDC264EVM for daisy-chain operation with four devices. ( https://www.ti.com/tool/DDC264EVM )

    Here are the subsequent questions we have about the datasheet guidelines:

    1.  How does the daisy-chained module receive configuration input (and its associated clock)? Does configuration of the second board happen at the same time of the first?

     >> To configure the register, the nRESET, CLK_CFG and DIN_CFG signals are used. Both daisy-chain devices can be programmed individually or separately depending on how these signals are connected for both modules. For the simplest setup, these signals can be connected together. In this case, all the devices will be configured to the same setting. Please refer to Figure 8 (page 12) in the datasheet for the register read and write operations using these signals. 

    2.  How does the daisy-chained module receive other signals like CLK, CONV and RESET to control integration and DVALID generation for that chip?

    >> For daisy-chain module, the CLK, CONV, RESET signals can be connected together for synchronous operation and a single DVALID signal from the daisy-chain module can be used as data retrieval detection. A rule of thumb is to use the DVALID from the last device in the CLK chain to avoid any race issue. Another option is to ORng the DVALID signals and use this signal as the data ready indicator. A simple solution is to add some delay to the DCLK after the DVALID signal to ensure that the data for devices in the daisy-chain is ready. 

    3.  When the DDC232 connected to the FPGA outputs DVALID – what does that mean for the other DDC232? The datasheet does not appear to show how DVALID is cascaded across converters. I would suspect that a DVALID means that both DDC232s are ready to send data?

    >> The DVALID signal doesn’t cascade across the devices, only one DVALID signal is needed for the FPGA to indicate the data is ready for retrieval (See reply on Question 2 for more detail).

    4.  Are the outputs of the configuration read-back and measurement readout cycle ordered automatically? That is, the output of the DDC232 connected to FPGA is then followed by the output of the daisy-chained module (or the other way round).

    >> The configuration readback is done using the configuration register read and write operation (see Question 1) which is separate from the measurement readout cycle.