Im prototyping a design. The ADS8167 is hand-soldered to a QFN adapter. The part is on a breadboard attached to a Nucleo H743Z. I am not getting recognizable data on the SDO line. I know this is my problem - Im just wondering if this SDO pattern is familiar to anyone.
The SDO line is inconsistent. I havent been able to find a regular pattern. I have read other comments. My lines seem to be at the right voltage:
Pin 3 - REFIO Voltage: 4.11
Pin 2 - DeCap voltage: 2.75
Pin 29 - Reset voltage: 3.28
The Ready line seems to follow Reset and SS like it should.
basic schematic and logic analyzer traces attached. Excuse my lame schematic. Logic analyzer traces that Im attaching are NOP commands. I cant get valid data when I read. What I find interesting is that *sometimes* the SDO line goes high during the NOP. I have other traces, but thought this would be a good starting point.
Any help gets a beer if you are in the Bay Area Ca.
Larry