using own board with 8 lane configuration and JMODE 30. The clock to the device is at 5.12 GHz and the expected SerDes rate is 16.896 Gbits/Sec.
is this correct?
the receiver in the FPGA is unable to find the 64b/66b header.
i have tried with a reduced sample rate of 3.9 GHz and Serdes rate of 12.87 Gbits/Sec and with the same results.
the data sheets does not give a direct equation for the serial rate.
could anyone who has successfully used this mode help please?
