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ADC34J44EVM: Confirmation with LMK048282 to generate JESD204 clock for ADC34J44EVM

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Replies: 4

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Part Number: ADC34J44EVM

Hi team,

We have a customer inquiry below and we need your help for confirmation:

The customer is going to evaluate the ADC34J44 with the EVM ADC34J44EVM with their own FMC board (which embeds an FPGA). In the schematic of the ADC34J44EVM TI adds the LMK048282 to generate JESD204 clock.
1. Is the sync input of this component mandatory to use the ADC?
2. The ADC is in 1.8V for the digital interface. But it seems that the LMK04828 is in 3.3V. Their FPGA is only in 1.8V. Could you confirm that the outputs of the LMK component are in 3.3V or they can program them?

From my early researching, question number 2 answer should be the LMK supply is 3.3V as per the datasheet but your answer is very much appreciated.

Thanks,

Jonathan

  • Hi team,

    Any update on this inquiry?

    Regards,

    Jonathan

  • In reply to Jonathan Geronga:

    Hey Johnathan, 

    I am looking into this. I will have a response for you by the end of the day. 

    Thanks

    Yusuf

  • In reply to Yusuf%20Agoro:

    Hi Yusuf,

    Thank you very much for your response.

    We are looking forward to your updates,

    Regards,

    Jonathan

  • In reply to Yusuf%20Agoro:

    Hey Johnathan, 

    1. Yes Sync is required for JESD204b protocol. 

    2. The LMK outputs can be AC coupled and also support LVDS. This should be compatible with customers FPGA. 

    Thanks

    Yusuf

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